Core Peripherals

Content
	Generic Interrupt Controller Functions
	The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC).
	L1 Cache Functions
	L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache.
	L2C-310 Cache Controller Functions
	L2C-310 Cache Controller gives access to functions for level 2 cache maintenance. Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual.
	Generic Physical Timer Functions
	Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices. Reference: Cortex-A7 MPCore Technical Reference Manual.
	Private Timer Functions
	Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices. References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual.
	Memory Management Unit Functions
	MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map. Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition.
	Floating Point Unit Functions
	FPU Functions enable the use of Floating Point instructions and extensions. Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition.

Description

Hardware Abstraction Layer. The Core-A function interface contains:

• Floating Point Unit Functions
• Generic Interrupt Controller Functions
• L1 Cache Functions
• L2C-310 Cache Controller Functions
• Memory Management Unit Functions
• Generic Physical Timer Functions
• Private Timer Functions