Version | Description |
V1.2.1 |
|
V1.2.0 |
-
Fixed GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR for compliance with all GIC specification versions.
-
Added missing DSP intrinsics.
-
Reworked assembly intrinsics: volatile, barriers and clobbers.
|
V1.1.4 |
|
V1.1.3 |
|
V1.1.2 |
-
Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.
-
Fixed co-processor register access macros for Arm Compiler 5.
|
V1.1.1 |
-
Refactored L1 cache maintenance to be compiler agnostic.
|
V1.1.0 |
-
Added compiler_iccarm.h for IAR compiler.
-
Added missing core access functions for Arm Compiler 5.
-
Aligned access function to coprocessor 15.
-
Additional generic Timer functions.
-
Bug fixes and minor enhancements.
|
V1.0.0 | Initial Release for Cortex-A5/A7/A9 processors. |