Hardware Requirements

The following section lists the hardware requirements for RTX v5 on the various supported target processors:

Processor Requirements

RTX assumes a fully functionable processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.

Cortex-M0/M0+/M23 target processor

Hardware Requirement	Description
SysTick timer	The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the OS Tick API
Exception Handler	RTX implements exception handlers for SVC, PendSV, and SysTick interrupt
Core Registers	The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK
System Control Block (SBC)	To control and setup the processor exceptions including PendSV and SVC
Interrupt Control	The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register.

The RTX implements interfaces to the processor hardware in following files:

• irq_armv6m.S defines exception handlers for Cortex-M0/M0+
• irq_armv8mbl.S defines exception handlers for Cortex-M23
• rtx_core_cm.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
• os_tick.h is the OS Tick API that defines the interface functions to the SysTick timer.

Note

• The CMSIS-Core variable SystemCoreClock is used by RTX to configure the SysTick timer.

Cortex-M3/M4/M7/M33/M35P target processor

RTX assumes a fully function-able processor and uses the following hardware features:

Hardware Item	Requirement Description
SysTick timer	The SysTick timer shall be available in the processor.
System Exceptions	The RTX requires SVC, PendSV, and SysTick exceptions and implements corresponding exception handlers.
Core Registers	The RTX uses CONTROL, IPSR , PRIMASK and BASEPRI core registers for reading processor status.
System Control Block (SCB)	The RTX uses SCB registers to control and setup the processor system exceptions including PendSV and SVC.
NVIC Interface	CMSIS-Core function NVIC_GetPriorityGrouping is used by the RTX to setup interrupt priorities.
LDREX, STREX instructions	Exclusive access instructions LDREX and STREX are used to implement atomic execution without disabling interrupts.

The interface files to the processor hardware are:

• irq_armv7m.S defines exception handlers for Cortex-M3 and Cortex-M4/M7.
• irq_armv8mml.S defines exception handlers for Cortex-M33/M35P
• rtx_core_cm.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
• os_tick.h is the OS Tick API that defines the interface functions to the SysTick timer.

Note

• The CMSIS-Core variable SystemCoreClock is used by RTX to configure the SysTick timer.

Cortex-A5/A7/A9 target processor

Hardware Requirement	Description
Timer Peripheral	An arbitrary timer peripheral generates the kernel tick interrupts. The interfaces for Cortex-A Generic Timer and Private Timer are implemented in os_tick_gtim.c and os_tick_ptim.c using the OS Tick API
Exception Handler	RTX implements exception handlers for SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction interrupt.
Core Registers	The processor status is read using the following core registers: CPSR, CPACR and FPSCR.
LDREX, STREX instruction	Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions.
Interrupt Controller	An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in irq_ctrl_gic.c using the IRQ Controller API.

The interface files to the processor hardware are:

• irq_armv7a.S defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.
• rtx_core_ca.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
• os_tick.h is the OS Tick API that defines the interface functions to the timer peripheral.
• irq_ctrl.h is the IRQ Controller API that defines the interface functions to the interrupt controller.

Note

• The CMSIS-Core variable SystemCoreClock is used by RTX to configure the timer peripheral.

Memory Requirements

RTX requires RAM memory that is accessible with contiguous linear addressing. When memory is split across multiple memory banks, some systems do not accept multiple load or store operations on this memory blocks.

RTX does not implement any confidence test for memory validation. This should be implemented by an user-supplied software test library.