Compute Library
 21.05
CPPTypes.cpp
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2  * Copyright (c) 2018-2021 Arm Limited.
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4  * SPDX-License-Identifier: MIT
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24 
26 
27 #include "arm_compute/core/Error.h"
28 
29 #if !defined(BARE_METAL)
30 #include <sched.h>
31 #endif /* defined(BARE_METAL) */
32 
33 using namespace arm_compute;
34 
35 void CPUInfo::set_fp16(const bool fp16)
36 {
37  _fp16 = fp16;
38 }
39 
40 void CPUInfo::set_dotprod(const bool dotprod)
41 {
42  _dotprod = dotprod;
43 }
44 
45 void CPUInfo::set_sve(const bool sve)
46 {
47  _sve = sve;
48 }
49 
50 void CPUInfo::set_cpu_model(unsigned int cpuid, CPUModel model)
51 {
52  ARM_COMPUTE_ERROR_ON(cpuid >= _percpu.size());
53  if(_percpu.size() > cpuid)
54  {
55  _percpu[cpuid] = model;
56  }
57 }
58 
59 unsigned int CPUInfo::get_cpu_num() const
60 {
61  return _percpu.size();
62 }
63 
64 bool CPUInfo::has_sve() const
65 {
66  return _sve;
67 }
68 
69 bool CPUInfo::has_fp16() const
70 {
71  return _fp16;
72 }
73 
75 {
76  return _dotprod;
77 }
78 
79 CPUModel CPUInfo::get_cpu_model(unsigned int cpuid) const
80 {
81  if(cpuid < _percpu.size())
82  {
83  return _percpu[cpuid];
84  }
85  return CPUModel::GENERIC;
86 }
87 
88 unsigned int CPUInfo::get_L1_cache_size() const
89 {
90  return _L1_cache_size;
91 }
92 
93 void CPUInfo::set_L1_cache_size(unsigned int size)
94 {
95  _L1_cache_size = size;
96 }
97 
98 unsigned int CPUInfo::get_L2_cache_size() const
99 {
100  return _L2_cache_size;
101 }
102 
103 void CPUInfo::set_L2_cache_size(unsigned int size)
104 {
105  _L2_cache_size = size;
106 }
107 
108 void CPUInfo::set_cpu_num(unsigned int cpu_count)
109 {
110  _percpu.resize(cpu_count);
111 }
112 
114  : _percpu(1)
115 {
116  // The core library knows nothing about the CPUs so we set only 1 CPU to be generic.
117  // The runtime NESCheduler will initialise this vector with the correct CPU models.
118  // See void detect_cpus_configuration(CPUInfo &cpuinfo) in CPPUtils.h
119  _percpu[0] = CPUModel::GENERIC;
120 }
121 
123 {
124 #if defined(BARE_METAL) || defined(__APPLE__) || (!defined(__arm__) && !defined(__aarch64__))
125  return get_cpu_model(0);
126 #else /* defined(BARE_METAL) || defined(__APPLE__) || (!defined(__arm__) && !defined(__aarch64__)) */
127  return get_cpu_model(sched_getcpu());
128 #endif /* defined(BARE_METAL) || defined(__APPLE__) || (!defined(__arm__) && !defined(__aarch64__)) */
129 }
void set_L2_cache_size(unsigned int size)
Set the L2 cache size.
Definition: CPPTypes.cpp:103
bool has_sve() const
Checks if the cpu model supports sve.
Definition: CPPTypes.cpp:64
CPUInfo()
Constructor.
Definition: CPPTypes.cpp:113
bool has_fp16() const
Checks if the cpu model supports fp16.
Definition: CPPTypes.cpp:69
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
CPUModel
CPU models - we only need to detect CPUs we have microarchitecture-specific code for.
Definition: CPPTypes.h:40
Copyright (c) 2017-2021 Arm Limited.
bool has_dotprod() const
Checks if the cpu model supports dot product.
Definition: CPPTypes.cpp:74
void set_cpu_model(unsigned int cpuid, CPUModel model)
Set the cpumodel for a given cpu core.
Definition: CPPTypes.cpp:50
unsigned int get_cpu_num() const
Return the maximum number of CPUs present.
Definition: CPPTypes.cpp:59
unsigned int get_L1_cache_size() const
Gets the L1 cache size.
Definition: CPPTypes.cpp:88
unsigned int get_L2_cache_size() const
Gets the L2 cache size.
Definition: CPPTypes.cpp:98
void set_sve(const bool sve)
Set sve support.
Definition: CPPTypes.cpp:45
CPUModel get_cpu_model() const
Gets the current thread's cpu model.
Definition: CPPTypes.cpp:122
void set_L1_cache_size(unsigned int size)
Set the L1 cache size.
Definition: CPPTypes.cpp:93
void set_dotprod(const bool dotprod)
Set dot product support.
Definition: CPPTypes.cpp:40
void set_fp16(const bool fp16)
Set fp16 support.
Definition: CPPTypes.cpp:35
void set_cpu_num(unsigned int cpu_count)
Set max number of cpus.
Definition: CPPTypes.cpp:108