Compute Library
 22.02
CpuActivationKernel.cpp
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1 /*
2  * Copyright (c) 2017-2022 Arm Limited.
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25 
28 #include "arm_compute/core/Utils.h"
29 #include "src/core/CPP/Validate.h"
32 
35 
36 #include <array>
37 
38 namespace arm_compute
39 {
40 namespace cpu
41 {
42 namespace kernels
43 {
44 namespace
45 {
46 static const std::vector<CpuActivationKernel::ActivationKernel> available_kernels =
47 {
48  {
49  "sve_fp16_activation",
50  [](const DataTypeISASelectorData & data) { return data.dt == DataType::F16 && data.isa.sve; },
52  },
53  {
54  "sve_fp32_activation",
55  [](const DataTypeISASelectorData & data) { return data.dt == DataType::F32 && data.isa.sve; },
57  },
58  {
59  "neon_fp16_activation",
60  [](const DataTypeISASelectorData & data) { return data.dt == DataType::F16 && data.isa.fp16; },
62  },
63  {
64  "neon_fp32_activation",
65  [](const DataTypeISASelectorData & data) { return data.dt == DataType::F32; },
67  },
68  {
69  "sve2_qu8_activation",
70  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8 && data.isa.sve2; },
72  },
73  {
74  "sve2_qs8_activation",
75  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8_SIGNED && data.isa.sve2; },
77  },
78  {
79  "sve2_qs16_activation",
80  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QSYMM16 && data.isa.sve2; },
82  },
83  {
84  "neon_qu8_activation",
85  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8; },
87  },
88  {
89  "neon_qs8_activation",
90  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8_SIGNED; },
92  },
93  {
94  "neon_qs16_activation",
95  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QSYMM16; },
97  },
98 };
99 
100 /* Supported activation in the 8-bit integer domain */
101 static const std::array<ActivationLayerInfo::ActivationFunction, 7> qasymm8_activations =
102 {
110 };
111 /* Supported activation in the 16-bit integer domain */
112 static const std::array<ActivationLayerInfo::ActivationFunction, 3> qsymm16_activations =
113 {
117 };
118 
119 Status validate_arguments(const ITensorInfo *src, const ITensorInfo *dst, const ActivationLayerInfo &activation_info)
120 {
123 
124  const auto *uk = CpuActivationKernel::get_implementation(DataTypeISASelectorData{ src->data_type(), CPUInfo::get().get_isa() });
125 
126  ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
127 
128  const DataType data_type = src->data_type();
129  const QuantizationInfo &oq_info = (dst != nullptr) ? dst->quantization_info() : src->quantization_info();
130  const ActivationLayerInfo::ActivationFunction f_act = activation_info.activation();
131 
132  ARM_COMPUTE_RETURN_ERROR_ON_MSG(is_data_type_quantized_asymmetric(data_type) && (std::find(std::begin(qasymm8_activations), std::end(qasymm8_activations), f_act) == std::end(qasymm8_activations)),
133  "For QASYMM8 only hard swish, leaky relu, tanh, logistic, relu and lower/upper bounded relu are supported");
134 
135  ARM_COMPUTE_RETURN_ERROR_ON_MSG(is_data_type_quantized_symmetric(data_type) && (std::find(std::begin(qsymm16_activations), std::end(qsymm16_activations), f_act) == std::end(qsymm16_activations)),
136  "For QSYMM16 only tanh and logistic are supported");
138  && (oq_info != QuantizationInfo(1.f / 128.f, 128)));
140  && (oq_info != QuantizationInfo(1.f / 256.f, 0)));
141 
142  ARM_COMPUTE_RETURN_ERROR_ON(data_type == DataType::QASYMM8_SIGNED && (f_act == ActivationLayerInfo::ActivationFunction::TANH) && (oq_info != QuantizationInfo(1.f / 128.f, 0)));
143  ARM_COMPUTE_RETURN_ERROR_ON(data_type == DataType::QASYMM8_SIGNED && (f_act == ActivationLayerInfo::ActivationFunction::LOGISTIC) && (oq_info != QuantizationInfo(1.f / 256.f, -128)));
144 
145  ARM_COMPUTE_RETURN_ERROR_ON(is_data_type_quantized_symmetric(data_type) && (f_act == ActivationLayerInfo::ActivationFunction::TANH) && (oq_info != QuantizationInfo(1.f / 32768.f, 0)));
146  ARM_COMPUTE_RETURN_ERROR_ON(is_data_type_quantized_symmetric(data_type) && (f_act == ActivationLayerInfo::ActivationFunction::LOGISTIC) && (oq_info != QuantizationInfo(1.f / 32768.f, 0)));
147 
148  // Checks performed when dst is configured
149  if((dst != nullptr) && (dst->total_size() != 0))
150  {
153  }
154 
155  return Status{};
156 }
157 
158 std::pair<Status, Window> validate_and_configure_window(const ITensorInfo *src, ITensorInfo *dst)
159 {
160  // Configure kernel window
161  Window win = calculate_max_window(*src, Steps());
162 
163  if(dst != nullptr)
164  {
165  // dst auto inizialitation if not yet initialized
166  auto_init_if_empty(*dst, *src->clone());
167  }
168 
169  return std::make_pair(Status{}, win);
170 }
171 } // namespace
172 
174 {
176  ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src, dst, activation_info));
177 
179 
181 
182  _act_info = activation_info;
183  _run_method = uk->ukernel;
184  _name = std::string("CpuActivationKernel").append("/").append(uk->name);
185 
186  // Configure kernel window
187  auto win_config = validate_and_configure_window(src, dst);
188  ARM_COMPUTE_ERROR_THROW_ON(win_config.first);
189  ICPPKernel::configure(win_config.second);
190 }
191 
193 {
194  ARM_COMPUTE_UNUSED(act_info);
195  ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src, dst, act_info));
196  ARM_COMPUTE_RETURN_ON_ERROR(validate_and_configure_window(src->clone().get(), (dst != nullptr) ? dst->clone().get() : nullptr).first);
197 
198  return Status{};
199 }
200 
201 size_t CpuActivationKernel::get_mws(const CPUInfo &platform, size_t thread_count) const
202 {
203  ARM_COMPUTE_UNUSED(thread_count);
204  ARM_COMPUTE_UNUSED(platform);
205 
207 }
208 
210 {
211  // Early exit on disabled activation
212  if(!_act_info.enabled())
213  {
214  return;
215  }
216 
217  ARM_COMPUTE_UNUSED(info);
220 
221  ARM_COMPUTE_ERROR_ON(tensors.empty());
222  ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
223 
224  const ITensor *src = tensors.get_const_tensor(TensorType::ACL_SRC);
225  ITensor *dst = tensors.get_tensor(TensorType::ACL_DST);
226 
227  _run_method(src, dst, _act_info, window);
228 }
229 
230 const char *CpuActivationKernel::name() const
231 {
232  return _name.c_str();
233 }
234 
235 const std::vector<CpuActivationKernel::ActivationKernel> &CpuActivationKernel::get_available_kernels()
236 {
237  return available_kernels;
238 }
239 } // namespace kernels
240 } // namespace cpu
241 } // namespace arm_compute
Window calculate_max_window(const ValidRegion &valid_region, const Steps &steps, bool skip_border, BorderSize border_size)
const Window & window() const
The maximum window the kernel can be executed on.
Definition: IKernel.cpp:28
void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override
Execute the kernel on the passed window.
quantized, symmetric fixed-point 16-bit number
static const auto * get_implementation(const SelectorType &selector, KernelSelectionType selection_type=KernelSelectionType::Supported)
Micro-kernel selector.
Definition: ICpuKernel.h:53
void configure(const ITensorInfo *src, ITensorInfo *dst, ActivationLayerInfo activation_info)
Configure kernel for a given list of arguments.
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:115
#define REGISTER_FP16_NEON(func_name)
Definition: Registrars.h:48
bool enabled() const
Check if initialised.
Definition: Types.h:1559
void sve2_qasymm8_signed_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
#define REGISTER_QSYMM16_SVE2(func_name)
Definition: Registrars.h:141
bool empty() const
Checks if pack is empty.
Definition: ITensorPack.cpp:80
static const std::vector< ActivationKernel > & get_available_kernels()
#define REGISTER_FP32_NEON(func_name)
Definition: Registrars.h:74
#define ARM_COMPUTE_RETURN_ON_ERROR(status)
Checks if a status contains an error and returns it.
Definition: Error.h:204
virtual DataType data_type() const =0
Data type used for each element of the tensor.
1 channel, 1 F32 per channel
void neon_qasymm8_signed_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
#define REGISTER_FP32_SVE(func_name)
Definition: Registrars.h:75
void neon_fp16_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
#define REGISTER_QASYMM8_SIGNED_NEON(func_name)
Definition: Registrars.h:96
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
#define ARM_COMPUTE_ERROR_THROW_ON(status)
Definition: Error.h:455
quantized, asymmetric fixed-point 16-bit number
Status class.
Definition: Error.h:52
void sve2_qasymm8_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
bool is_data_type_quantized_symmetric(DataType dt)
Check if a given data type is of symmetric quantized type.
Definition: Utils.h:1054
#define ARM_COMPUTE_RETURN_ERROR_ON(cond)
If the condition is true, an error is returned.
Definition: Error.h:296
Activation Layer Information class.
Definition: Types.h:1509
Interface for CPU tensor.
Definition: ITensor.h:36
SimpleTensor< float > src
Definition: DFT.cpp:155
const char * name() const override
Name of the kernel.
Copyright (c) 2017-2021 Arm Limited.
ActivationFunction
Available activation functions.
Definition: Types.h:1513
1 channel, 1 F16 per channel
const DataType data_type
Definition: Im2Col.cpp:150
const ITensor * get_const_tensor(int id) const
Get constant tensor of a given id.
Definition: ITensorPack.cpp:54
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
#define REGISTER_QASYMM8_NEON(func_name)
Definition: Registrars.h:117
quantized, asymmetric fixed-point 8-bit number unsigned
#define REGISTER_QSYMM16_NEON(func_name)
Definition: Registrars.h:139
bool auto_init_if_empty(ITensorInfo &info, const TensorShape &shape, int num_channels, DataType data_type, QuantizationInfo quantization_info=QuantizationInfo())
Auto initialize the tensor info (shape, number of channels and data type) if the current assignment i...
virtual std::unique_ptr< T > clone() const =0
Provide a clone of the current object of class T.
#define REGISTER_QASYMM8_SIGNED_SVE2(func_name)
Definition: Registrars.h:98
void end(TokenStream &in, bool &valid)
Definition: MLGOParser.cpp:290
#define ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(k)
Definition: Validate.h:915
void neon_fp32_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
Definition: fp32.cpp:34
bool is_data_type_quantized_asymmetric(DataType dt)
Check if a given data type is of asymmetric quantized type.
Definition: Utils.h:1018
void neon_qasymm8_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
Definition: qasymm8.cpp:39
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
ITensor * get_tensor(int id)
Get tensor of a given id from the pac.
Definition: ITensorPack.cpp:64
Information about executing thread and CPU.
Definition: CPPTypes.h:169
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_SHAPES(...)
Definition: Validate.h:439
#define REGISTER_FP16_SVE(func_name)
Definition: Registrars.h:49
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:541
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:788
#define ARM_COMPUTE_RETURN_ERROR_ON_MSG(cond, msg)
If the condition is true, an error is returned.
Definition: Error.h:244
Tensor packing service.
Definition: ITensorPack.h:39
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:157
void sve_fp16_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
void sve2_qsymm16_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
quantized, asymmetric fixed-point 8-bit number signed
static CPUInfo & get()
Access the KernelLibrary singleton.
Definition: CPPTypes.cpp:40
static Status validate(const ITensorInfo *src, const ITensorInfo *dst, const ActivationLayerInfo &act_info)
Static function to check if given info will lead to a valid configuration.
size_t get_mws(const CPUInfo &platform, size_t thread_count) const override
Return minimum workload size of the relevant kernel.
#define REGISTER_QASYMM8_SVE2(func_name)
Definition: Registrars.h:119
DataType
Available data types.
Definition: Types.h:79
void neon_qsymm16_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)
Definition: qsymm16.cpp:40
Describe a multidimensional execution window.
Definition: Window.h:39
#define ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(f, s)
Definition: Validate.h:201
static constexpr size_t default_mws
Definition: ICPPKernel.h:41
cpuinfo::CpuIsaInfo get_isa() const
Gets the current cpu&#39;s ISA information.
Definition: CPPTypes.cpp:114
void sve_fp32_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window)