Compute Library
 22.11
CpuAddKernel.cpp
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25 
29 #include "src/core/CPP/Validate.h"
34 #include <array>
35 
36 namespace arm_compute
37 {
38 namespace cpu
39 {
40 namespace kernels
41 {
42 namespace
43 {
44 static const std::vector<CpuAddKernel::AddKernel> available_kernels =
45 {
46  {
47  "neon_qu8_add_fixedpoint",
48  [](const CpuAddKernelDataTypeISASelectorData & data)
49  {
50  return (data.dt == DataType::QASYMM8) && data.can_use_fixedpoint;
51  },
53  },
54  {
55  "neon_qs8_add_fixedpoint",
56  [](const CpuAddKernelDataTypeISASelectorData & data)
57  {
58  return (data.dt == DataType::QASYMM8_SIGNED) && data.can_use_fixedpoint;
59  },
61  },
62  {
63  "sve2_qu8_add",
64  [](const CpuAddKernelDataTypeISASelectorData & data)
65  {
66  return (data.dt == DataType::QASYMM8) && data.isa.sve2;
67  },
69  },
70  {
71  "sve2_qs8_add",
72  [](const CpuAddKernelDataTypeISASelectorData & data)
73  {
74  return (data.dt == DataType::QASYMM8_SIGNED) && data.isa.sve2;
75  },
77  },
78  {
79  "sve2_qs16_add",
80  [](const CpuAddKernelDataTypeISASelectorData & data)
81  {
82  return (data.dt == DataType::QSYMM16) && data.isa.sve2;
83  },
85  },
86  {
87  "sve_fp32_add",
88  [](const CpuAddKernelDataTypeISASelectorData & data)
89  {
90  return (data.dt == DataType::F32) && data.isa.sve;
91  },
93  },
94  {
95  "sve_fp16_add",
96  [](const CpuAddKernelDataTypeISASelectorData & data)
97  {
98  return (data.dt == DataType::F16) && data.isa.sve && data.isa.fp16;
99  },
101  },
102  {
103  "sve_u8_add",
104  [](const CpuAddKernelDataTypeISASelectorData & data)
105  {
106  return (data.dt == DataType::U8) && data.isa.sve;
107  },
109  },
110  {
111  "sve_s16_add",
112  [](const CpuAddKernelDataTypeISASelectorData & data)
113  {
114  return (data.dt == DataType::S16) && data.isa.sve;
115  },
117  },
118  {
119  "sve_s32_add",
120  [](const CpuAddKernelDataTypeISASelectorData & data)
121  {
122  return (data.dt == DataType::S32) && data.isa.sve;
123  },
125  },
126  {
127  "neon_fp32_add",
128  [](const CpuAddKernelDataTypeISASelectorData & data) { return (data.dt == DataType::F32); },
130  },
131  {
132  "neon_fp16_add",
133  [](const CpuAddKernelDataTypeISASelectorData & data)
134  {
135  return (data.dt == DataType::F16) && data.isa.fp16;
136  },
138  },
139  {
140  "neon_u8_add",
141  [](const CpuAddKernelDataTypeISASelectorData & data) { return (data.dt == DataType::U8); },
143  },
144  {
145  "neon_s16_add",
146  [](const CpuAddKernelDataTypeISASelectorData & data) { return (data.dt == DataType::S16); },
148  },
149  {
150  "neon_s32_add",
151  [](const CpuAddKernelDataTypeISASelectorData & data) { return (data.dt == DataType::S32); },
153  },
154  {
155  "neon_qu8_add",
156  [](const CpuAddKernelDataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8); },
158  },
159  {
160  "neon_qs8_add",
161  [](const CpuAddKernelDataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8_SIGNED); },
163  },
164  {
165  "neon_qs16_add",
166  [](const CpuAddKernelDataTypeISASelectorData & data) { return (data.dt == DataType::QSYMM16); },
168  }
169 };
170 
171 Status validate_arguments(const ITensorInfo &src0, const ITensorInfo &src1, const ITensorInfo &dst, ConvertPolicy policy)
172 {
173  ARM_COMPUTE_UNUSED(policy);
174 
180 
181  const TensorShape out_shape = TensorShape::broadcast_shape(src0.tensor_shape(), src1.tensor_shape());
182 
183  ARM_COMPUTE_RETURN_ERROR_ON_MSG(out_shape.total_size() == 0, "Inputs are not broadcast compatible");
184  ARM_COMPUTE_RETURN_ERROR_ON_MSG((src0.tensor_shape().x() != src1.tensor_shape().x()) && ((src0.data_type() != src1.data_type()) || (src0.data_type() != dst.data_type())
185  || (src1.data_type() != dst.data_type())),
186  "Broadcasting across width is supported on configurations where all tensors have the same data type");
187 
188  // Validate in case of configured dst
189  if(dst.total_size() > 0)
190  {
192  ARM_COMPUTE_RETURN_ERROR_ON_MSG(detail::have_different_dimensions(out_shape, dst.tensor_shape(), 0),
193  "Wrong shape for dst");
194  }
195 
196  const auto can_use_fixedpoint = add_q8_neon_fixedpoint_possible(&src0, &src1, &dst);
197  const auto uk = CpuAddKernel::get_implementation<CpuAddKernelDataTypeISASelectorData>(CpuAddKernelDataTypeISASelectorData{ src0.data_type(),
198  CPUInfo::get().get_isa(), can_use_fixedpoint });
199  ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
200 
201  return Status{};
202 }
203 } // namespace
204 
205 void CpuAddKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, ITensorInfo *dst, ConvertPolicy policy)
206 {
207  ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst);
208  ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(*src0, *src1, *dst, policy));
209 
210  const auto can_use_fixedpoint = add_q8_neon_fixedpoint_possible(src0, src1, dst);
211  const auto uk = CpuAddKernel::get_implementation<CpuAddKernelDataTypeISASelectorData>(CpuAddKernelDataTypeISASelectorData{ src0->data_type(),
212  CPUInfo::get().get_isa(), can_use_fixedpoint });
213 
215 
216  _policy = policy;
217  _run_method = uk->ukernel;
218  _name = std::string("CpuAddKernel").append("/").append(uk->name);
219 
220  // Auto initialize dst if not initialized
221  const TensorShape &out_shape = TensorShape::broadcast_shape(src0->tensor_shape(), src1->tensor_shape());
222  set_shape_if_empty(*dst, out_shape);
223  set_data_type_if_unknown(*dst, src0->data_type());
224 
225  // Configure kernel window
226  Window win;
227  std::tie(win, _split_dimension) = calculate_squashed_or_max_window(*src0, *src1);
228 
229  ICpuKernel::configure(win);
230 }
231 
232 Status CpuAddKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *dst, ConvertPolicy policy)
233 {
234  ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst);
235 
236  ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(*src0, *src1, *dst, policy));
237 
238  return Status{};
239 }
240 
242 {
243  ARM_COMPUTE_UNUSED(info);
246 
247  ARM_COMPUTE_ERROR_ON(tensors.empty());
248  ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
249 
250  const ITensor *src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
251  const ITensor *src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
252  ITensor *dst = tensors.get_tensor(TensorType::ACL_DST);
253 
254  _run_method(src0, src1, dst, _policy, window);
255 }
256 
257 const char *CpuAddKernel::name() const
258 {
259  return _name.c_str();
260 }
261 
262 const std::vector<CpuAddKernel::AddKernel> &CpuAddKernel::get_available_kernels()
263 {
264  return available_kernels;
265 }
266 
267 size_t CpuAddKernel::get_mws(const CPUInfo &platform, size_t thread_count) const
268 {
269  ARM_COMPUTE_UNUSED(thread_count);
270  ARM_COMPUTE_UNUSED(platform);
271 
273 }
274 
275 } // namespace kernels
276 } // namespace cpu
277 } // namespace arm_compute
const Window & window() const
The maximum window the kernel can be executed on.
Definition: IKernel.cpp:28
Shape of a tensor.
Definition: TensorShape.h:39
quantized, symmetric fixed-point 16-bit number
bool set_data_type_if_unknown(ITensorInfo &info, DataType data_type)
Set the data type and number of channels to the specified value if the current data type is unknown...
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:115
#define REGISTER_FP16_NEON(func_name)
Definition: Registrars.h:48
void add_qasymm8_signed_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
#define REGISTER_QSYMM16_SVE2(func_name)
Definition: Registrars.h:141
bool empty() const
Checks if pack is empty.
Definition: ITensorPack.cpp:80
void add_fp16_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
void add_u8_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: integer.cpp:31
1 channel, 1 U8 per channel
void add_s32_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: integer.cpp:41
#define REGISTER_FP32_NEON(func_name)
Definition: Registrars.h:74
#define ARM_COMPUTE_RETURN_ON_ERROR(status)
Checks if a status contains an error and returns it.
Definition: Error.h:204
virtual DataType data_type() const =0
Data type used for each element of the tensor.
void add_qsymm16_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: qsymm16.cpp:37
1 channel, 1 F32 per channel
#define REGISTER_FP32_SVE(func_name)
Definition: Registrars.h:75
static TensorShape broadcast_shape(const Shapes &... shapes)
If shapes are broadcast compatible, return the broadcasted shape.
Definition: TensorShape.h:211
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
#define REGISTER_QASYMM8_SIGNED_NEON(func_name)
Definition: Registrars.h:96
void add_fp16_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
static const std::vector< AddKernel > & get_available_kernels()
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
#define ARM_COMPUTE_ERROR_THROW_ON(status)
Definition: Error.h:455
Status class.
Definition: Error.h:52
Status validate_arguments(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *dst, const PadStrideInfo &conv_info)
#define ARM_COMPUTE_RETURN_ERROR_ON(cond)
If the condition is true, an error is returned.
Definition: Error.h:296
Interface for CPU tensor.
Definition: ITensor.h:36
void add_s32_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: integer.cpp:43
Copyright (c) 2017-2022 Arm Limited.
1 channel, 1 F16 per channel
void add_qsymm16_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: qsymm16.cpp:35
void add_qasymm8_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: qasymm8.cpp:36
void add_s16_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: integer.cpp:36
#define REGISTER_INTEGER_NEON(func_name)
Definition: Registrars.h:171
#define ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(...)
Definition: Validate.h:159
void add_fp32_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: fp32.cpp:33
1 channel, 1 S32 per channel
const ITensor * get_const_tensor(int id) const
Get constant tensor of a given id.
Definition: ITensorPack.cpp:54
void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override
Execute the kernel on the passed window.
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
#define REGISTER_QASYMM8_NEON(func_name)
Definition: Registrars.h:117
virtual const TensorShape & tensor_shape() const =0
Size for each dimension of the tensor.
quantized, asymmetric fixed-point 8-bit number unsigned
template void add_q8_neon_fixedpoint< int8_t >(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
#define REGISTER_QSYMM16_NEON(func_name)
Definition: Registrars.h:139
#define REGISTER_INTEGER_SVE(func_name)
Definition: Registrars.h:172
void add_u8_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: integer.cpp:33
bool set_shape_if_empty(ITensorInfo &info, const TensorShape &shape)
Set the shape to the specified value if the current assignment is empty.
bool have_different_dimensions(const Dimensions< T > &dim1, const Dimensions< T > &dim2, unsigned int upper_dim)
Definition: Validate.h:47
#define REGISTER_QASYMM8_SIGNED_SVE2(func_name)
Definition: Registrars.h:98
void add_s16_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: integer.cpp:38
size_t get_mws(const CPUInfo &platform, size_t thread_count) const override
Return minimum workload size of the relevant kernel.
const char * name() const override
Name of the kernel.
#define ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(k)
Definition: Validate.h:915
1 channel, 1 S16 per channel
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
ITensor * get_tensor(int id)
Get tensor of a given id from the pac.
Definition: ITensorPack.cpp:64
Information about executing thread and CPU.
Definition: CPPTypes.h:179
void add_fp32_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: fp32.cpp:31
#define REGISTER_FP16_SVE(func_name)
Definition: Registrars.h:49
static Status validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *dst, ConvertPolicy policy)
Static function to check if given info will lead to a valid configuration.
void configure(const ITensorInfo *src0, const ITensorInfo *src1, ITensorInfo *dst, ConvertPolicy policy)
Initialise the kernel&#39;s input, dst and border mode.
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:541
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:788
void add_qasymm8_signed_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
std::pair< Window, size_t > calculate_squashed_or_max_window(const ITensorInfo &src0, const ITensorInfo &src1)
#define ARM_COMPUTE_RETURN_ERROR_ON_MSG(cond, msg)
If the condition is true, an error is returned.
Definition: Error.h:244
Tensor packing service.
Definition: ITensorPack.h:39
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:157
quantized, asymmetric fixed-point 8-bit number signed
static CPUInfo & get()
Access the KernelLibrary singleton.
Definition: CPPTypes.cpp:40
bool add_q8_neon_fixedpoint_possible(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *dst)
Definition: impl.cpp:131
#define REGISTER_QASYMM8_SVE2(func_name)
Definition: Registrars.h:119
void add_qasymm8_sve2(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: qasymm8.cpp:37
Describe a multidimensional execution window.
Definition: Window.h:39
ConvertPolicy
Policy to handle integer overflow.
Definition: Types.h:404
#define ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(f, s)
Definition: Validate.h:201
static constexpr size_t default_mws
Definition: ICPPKernel.h:41
cpuinfo::CpuIsaInfo get_isa() const
Gets the current cpu&#39;s ISA information.
Definition: CPPTypes.cpp:124
template void add_q8_neon_fixedpoint< uint8_t >(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)