Compute Library
 21.11
CpuAddKernel.cpp
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1 /*
2  * Copyright (c) 2021 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
5  *
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13  * The above copyright notice and this permission notice shall be included in all
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15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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22  * SOFTWARE.
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25 
29 #include "src/core/CPP/Validate.h"
35 
36 #include <array>
37 
38 namespace arm_compute
39 {
40 namespace cpu
41 {
42 namespace kernels
43 {
44 namespace
45 {
46 struct AddSelectorData
47 {
49  const CPUInfo &ci;
50 };
51 
54 struct AddKernel
55 {
56  const char *name;
57  const AddSelectorPtr is_selected;
58  AddKernelPtr ukernel;
59 };
60 
61 static const AddKernel available_kernels[] =
62 {
63 #if defined(ARM_COMPUTE_ENABLE_SVE2)
64  {
65  "sve2_qu8_add",
66  [](const AddSelectorData & data)
67  {
68  return (data.dt == DataType::QASYMM8) && data.ci.has_sve2();
69  },
70  REGISTER_QASYMM8_SVE(arm_compute::cpu::add_qasymm8_sve)
71  },
72  {
73  "sve2_qs8_add",
74  [](const AddSelectorData & data)
75  {
76  return (data.dt == DataType::QASYMM8_SIGNED) && data.ci.has_sve2();
77  },
78  REGISTER_QASYMM8_SIGNED_SVE(arm_compute::cpu::add_qasymm8_signed_sve)
79  },
80  {
81  "sve2_qs16_add",
82  [](const AddSelectorData & data)
83  {
84  return (data.dt == DataType::QSYMM16) && data.ci.has_sve2();
85  },
86  REGISTER_QSYMM16_SVE(arm_compute::cpu::add_qsymm16_sve)
87  },
88 #endif /* !defined(ARM_COMPUTE_ENABLE_SVE2) */
89 #if defined(ARM_COMPUTE_ENABLE_SVE)
90  {
91  "sve_fp32_add",
92  [](const AddSelectorData & data)
93  {
94  return (data.dt == DataType::F32) && data.ci.has_sve();
95  },
96  REGISTER_FP32_SVE(arm_compute::cpu::add_same_sve<float>)
97  },
98  {
99  "sve_fp16_add",
100  [](const AddSelectorData & data)
101  {
102  return (data.dt == DataType::F16) && data.ci.has_sve();
103  },
104  REGISTER_FP16_SVE(arm_compute::cpu::add_same_sve<float16_t>)
105  },
106  {
107  "sve_u8_add",
108  [](const AddSelectorData & data)
109  {
110  return (data.dt == DataType::U8) && data.ci.has_sve();
111  },
112  REGISTER_INTEGER_SVE(arm_compute::cpu::add_same_sve<uint8_t>)
113  },
114  {
115  "sve_s16_add",
116  [](const AddSelectorData & data)
117  {
118  return (data.dt == DataType::S16) && data.ci.has_sve();
119  },
120  REGISTER_INTEGER_SVE(arm_compute::cpu::add_same_sve<int16_t>)
121  },
122  {
123  "sve_s32_add",
124  [](const AddSelectorData & data)
125  {
126  return (data.dt == DataType::S32) && data.ci.has_sve();
127  },
128  REGISTER_INTEGER_SVE(arm_compute::cpu::add_same_sve<int32_t>)
129  },
130 #endif /* defined(ARM_COMPUTE_ENABLE_SVE) */
131 #if defined(ARM_COMPUTE_ENABLE_NEON)
132  {
133  "neon_fp32_add",
134  [](const AddSelectorData & data) { return (data.dt == DataType::F32); },
135  REGISTER_FP32_NEON(arm_compute::cpu::add_same_neon<float>)
136  },
137 #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
138  {
139  "neon_fp16_add",
140  [](const AddSelectorData & data)
141  {
142  return (data.dt == DataType::F16) && data.ci.has_fp16();
143  },
144  REGISTER_FP16_NEON(arm_compute::cpu::add_same_neon<float16_t>)
145  },
146 #endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) */
147  {
148  "neon_u8_add",
149  [](const AddSelectorData & data) { return (data.dt == DataType::U8); },
150  REGISTER_INTEGER_NEON(arm_compute::cpu::add_same_neon<uint8_t>)
151  },
152  {
153  "neon_s16_add",
154  [](const AddSelectorData & data) { return (data.dt == DataType::S16); },
155  REGISTER_INTEGER_NEON(arm_compute::cpu::add_same_neon<int16_t>)
156  },
157  {
158  "neon_s32_add",
159  [](const AddSelectorData & data) { return (data.dt == DataType::S32); },
160  REGISTER_INTEGER_NEON(arm_compute::cpu::add_same_neon<int32_t>)
161  },
162 #endif /* defined(ARM_COMPUTE_ENABLE_NEON) */
163 #if defined(ARM_COMPUTE_ENABLE_NEON) || defined(ARM_COMPUTE_ENABLE_SVE)
164  {
165  "neon_qu8_add",
166  [](const AddSelectorData & data) { return (data.dt == DataType::QASYMM8); },
168  },
169  {
170  "neon_qs8_add",
171  [](const AddSelectorData & data) { return (data.dt == DataType::QASYMM8_SIGNED); },
173  },
174  {
175  "neon_qs16_add",
176  [](const AddSelectorData & data) { return (data.dt == DataType::QSYMM16); },
178  },
179 #endif /* defined(ARM_COMPUTE_ENABLE_NEON) || defined(ARM_COMPUTE_ENABLE_SVE) */
180 };
181 
182 /** Micro-kernel selector
183  *
184  * @param[in] data Selection data passed to help pick the appropriate micro-kernel
185  *
186  * @return A matching micro-kernel else nullptr
187  */
188 const AddKernel *get_implementation(const CPUInfo &cpuinfo, DataType dt)
189 {
190  for(const auto &uk : available_kernels)
191  {
192  if(uk.is_selected({ dt, cpuinfo }))
193  {
194  return &uk;
195  }
196  }
197  return nullptr;
198 }
199 
200 Status validate_arguments(const ITensorInfo &src0, const ITensorInfo &src1, const ITensorInfo &dst, ConvertPolicy policy)
201 {
202  ARM_COMPUTE_UNUSED(policy);
203 
209 
210  const TensorShape out_shape = TensorShape::broadcast_shape(src0.tensor_shape(), src1.tensor_shape());
211 
212  ARM_COMPUTE_RETURN_ERROR_ON_MSG(out_shape.total_size() == 0, "Inputs are not broadcast compatible");
213  ARM_COMPUTE_RETURN_ERROR_ON_MSG((src0.tensor_shape().x() != src1.tensor_shape().x()) && ((src0.data_type() != src1.data_type()) || (src0.data_type() != dst.data_type())
214  || (src1.data_type() != dst.data_type())),
215  "Broadcasting across width is supported on configurations where all tensors have the same data type");
216 
217  // Validate in case of configured dst
218  if(dst.total_size() > 0)
219  {
221  ARM_COMPUTE_RETURN_ERROR_ON_MSG(detail::have_different_dimensions(out_shape, dst.tensor_shape(), 0),
222  "Wrong shape for dst");
223  }
224 
225  const auto *uk = get_implementation(CPUInfo::get(), src0.data_type());
226  ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
227 
228  return Status{};
229 }
230 
231 std::pair<Status, Window> validate_and_configure_window(const ITensorInfo &src0, const ITensorInfo &src1, ITensorInfo &dst)
232 {
233  const TensorShape &out_shape = TensorShape::broadcast_shape(src0.tensor_shape(), src1.tensor_shape());
234 
235  // Auto initialize dst if not initialized
236  set_shape_if_empty(dst, out_shape);
237  set_data_type_if_unknown(dst, src0.data_type());
238 
239  Window win = calculate_max_window(out_shape, Steps());
240 
241  // CpuAddKernel doesn't need padding so update_window_and_padding() can be skipped
242  return std::make_pair(Status{}, win);
243 }
244 } // namespace
245 
247 {
248  ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst);
249  ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(*src0, *src1, *dst, policy));
250 
251  const auto uk = get_implementation(CPUInfo::get(), src0->data_type());
253 
254  _policy = policy;
255  _run_method = uk->ukernel;
256  _name = std::string("CpuAddKernel").append("/").append(uk->name);
257 
258  // Configure kernel window
259  auto win_config = validate_and_configure_window(*src0, *src1, *dst);
260  ARM_COMPUTE_ERROR_THROW_ON(win_config.first);
261  ICpuKernel::configure(win_config.second);
262 }
263 
265 {
266  ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst);
267 
268  ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(*src0, *src1, *dst, policy));
269  ARM_COMPUTE_RETURN_ON_ERROR(validate_and_configure_window(*src0->clone(), *src1->clone(), *dst->clone()).first);
270 
271  return Status{};
272 }
273 
274 void CpuAddKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
275 {
276  ARM_COMPUTE_UNUSED(info);
279 
280  ARM_COMPUTE_ERROR_ON(tensors.empty());
281  ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
282 
283  const ITensor *src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
284  const ITensor *src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
286 
287  _run_method(src0, src1, dst, _policy, window);
288 }
289 
290 const char *CpuAddKernel::name() const
291 {
292  return _name.c_str();
293 }
294 
295 size_t CpuAddKernel::get_mws(const CPUInfo &platform, size_t thread_count) const
296 {
297  ARM_COMPUTE_UNUSED(platform, thread_count);
298 
300 }
301 
302 } // namespace kernels
303 } // namespace cpu
304 } // namespace arm_compute
Window calculate_max_window(const ValidRegion &valid_region, const Steps &steps, bool skip_border, BorderSize border_size)
const Window & window() const
The maximum window the kernel can be executed on.
Definition: IKernel.cpp:28
quantized, symmetric fixed-point 16-bit number
bool set_data_type_if_unknown(ITensorInfo &info, DataType data_type)
Set the data type and number of channels to the specified value if the current data type is unknown...
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:115
#define REGISTER_FP16_NEON(func_name)
Definition: Registrars.h:42
static constexpr size_t small_network_mws
Definition: ICPPKernel.h:42
bool empty() const
Checks if pack is empty.
Definition: ITensorPack.cpp:80
1 channel, 1 U8 per channel
#define REGISTER_FP32_NEON(func_name)
Definition: Registrars.h:61
AddKernelPtr ukernel
#define ARM_COMPUTE_RETURN_ON_ERROR(status)
Checks if a status contains an error and returns it.
Definition: Error.h:204
virtual DataType data_type() const =0
Data type used for each element of the tensor.
1 channel, 1 F32 per channel
#define REGISTER_FP32_SVE(func_name)
Definition: Registrars.h:62
static TensorShape broadcast_shape(const Shapes &... shapes)
If shapes are broadcast compatible, return the broadcasted shape.
Definition: TensorShape.h:211
#define REGISTER_QASYMM8_SVE(func_name)
Definition: Registrars.h:91
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
#define REGISTER_QASYMM8_SIGNED_NEON(func_name)
Definition: Registrars.h:76
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
#define ARM_COMPUTE_ERROR_THROW_ON(status)
Definition: Error.h:455
Status class.
Definition: Error.h:52
#define ARM_COMPUTE_RETURN_ERROR_ON(cond)
If the condition is true, an error is returned.
Definition: Error.h:296
decltype(strategy::transforms) typedef type
Interface for CPU tensor.
Definition: ITensor.h:36
Copyright (c) 2017-2021 Arm Limited.
1 channel, 1 F16 per channel
void add_qsymm16_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: qsymm16.cpp:35
void add_qasymm8_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
Definition: qasymm8.cpp:35
#define REGISTER_INTEGER_NEON(func_name)
Definition: Registrars.h:124
#define ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(...)
Definition: Validate.h:159
#define REGISTER_QASYMM8_SIGNED_SVE(func_name)
Definition: Registrars.h:77
1 channel, 1 S32 per channel
const ITensor * get_const_tensor(int id) const
Get constant tensor of a given id.
Definition: ITensorPack.cpp:54
void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override
Execute the kernel on the passed window.
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
#define REGISTER_QASYMM8_NEON(func_name)
Definition: Registrars.h:90
quantized, asymmetric fixed-point 8-bit number unsigned
#define REGISTER_QSYMM16_NEON(func_name)
Definition: Registrars.h:105
#define REGISTER_INTEGER_SVE(func_name)
Definition: Registrars.h:125
virtual std::unique_ptr< T > clone() const =0
Provide a clone of the current object of class T.
bool set_shape_if_empty(ITensorInfo &info, const TensorShape &shape)
Set the shape to the specified value if the current assignment is empty.
bool have_different_dimensions(const Dimensions< T > &dim1, const Dimensions< T > &dim2, unsigned int upper_dim)
Definition: Validate.h:47
size_t get_mws(const CPUInfo &platform, size_t thread_count) const override
Return minimum workload size of the relevant kernel.
const char * name() const override
Name of the kernel.
#define ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(k)
Definition: Validate.h:915
1 channel, 1 S16 per channel
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
ITensor * get_tensor(int id)
Get tensor of a given id from the pac.
Definition: ITensorPack.cpp:64
Information about executing thread and CPU.
Definition: CPPTypes.h:158
#define REGISTER_QSYMM16_SVE(func_name)
Definition: Registrars.h:106
#define REGISTER_FP16_SVE(func_name)
Definition: Registrars.h:43
static Status validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *dst, ConvertPolicy policy)
Static function to check if given info will lead to a valid configuration.
void configure(const ITensorInfo *src0, const ITensorInfo *src1, ITensorInfo *dst, ConvertPolicy policy)
Initialise the kernel&#39;s input, dst and border mode.
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:541
const CPUInfo & ci
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:788
void add_qasymm8_signed_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window)
#define ARM_COMPUTE_RETURN_ERROR_ON_MSG(cond, msg)
If the condition is true, an error is returned.
Definition: Error.h:244
Tensor packing service.
Definition: ITensorPack.h:39
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:157
quantized, asymmetric fixed-point 8-bit number signed
static CPUInfo & get()
Access the KernelLibrary singleton.
Definition: CPPTypes.cpp:39
const char * name
DataType
Available data types.
Definition: Types.h:79
const AddSelectorPtr is_selected
Describe a multidimensional execution window.
Definition: Window.h:39
ConvertPolicy
Policy to handle integer overflow.
Definition: Types.h:391
DataType dt
#define ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(f, s)
Definition: Validate.h:201