Compute Library
 22.11
CpuDirectConv3dKernel.cpp
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25 
26 #include "arm_compute/core/Error.h"
30 #include "arm_compute/core/Types.h"
31 #include "arm_compute/core/Utils.h"
34 #include "src/core/CPP/Validate.h"
39 
40 #include <algorithm>
41 
42 using namespace arm_compute::detail;
43 
44 namespace arm_compute
45 {
46 namespace cpu
47 {
48 namespace kernels
49 {
50 namespace
51 {
52 static const std::vector<CpuDirectConv3dKernel::DirectConv3dKernel> available_kernels =
53 {
54 #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
55  {
56  "neon_fp16_directconv3d",
57  [](const DataTypeISASelectorData & data) { return data.dt == DataType::F16 && data.isa.fp16; },
58  REGISTER_FP16_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float16_t>)
59  },
60 #endif /* !defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) */
61  {
62  "neon_fp32_directconv3d",
63  [](const DataTypeISASelectorData & data) { return data.dt == DataType::F32; },
64  REGISTER_FP32_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float>)
65  },
66  {
67  "neon_qasymm8_directconv3d",
68  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8; },
69  REGISTER_QASYMM8_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<uint8_t>)
70  },
71  {
72  "neon_qasymm8_signed_directconv3d",
73  [](const DataTypeISASelectorData & data) { return data.dt == DataType::QASYMM8_SIGNED; },
74  REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<int8_t>)
75  }
76 };
77 
78 Status validate_arguments(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info)
79 {
80  ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst);
81  ARM_COMPUTE_RETURN_ERROR_ON(src0->data_layout() != DataLayout::NDHWC);
86  ARM_COMPUTE_RETURN_ERROR_ON(conv_info.dilation != Size3D(1U, 1U, 1U));
87 
88  const auto *uk = CpuDirectConv3dKernel::get_implementation(DataTypeISASelectorData{ src0->data_type(), CPUInfo::get().get_isa() });
89 
90  ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
91 
92  const DataLayout data_layout = src0->data_layout();
93  const int channel_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::CHANNEL);
94 
95  // Weight layout is D, H, W, Cin, Cout
96  ARM_COMPUTE_RETURN_ERROR_ON(src1->num_dimensions() > 5);
97  ARM_COMPUTE_RETURN_ERROR_ON(src1->dimension(1) != src0->dimension(channel_idx));
98 
99  if(src2 != nullptr)
100  {
101  if(is_data_type_quantized(src0->data_type()))
102  {
104  }
105  else
106  {
108  }
109  ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->dimension(0) != src1->dimension(0), "Biases size and number of dst feature maps should match");
110  ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->num_dimensions() > 1, "Biases should be one dimensional");
111  }
112 
113  // Checks performed when output is configured
114  if(dst->total_size() != 0)
115  {
116  TensorShape output_shape = misc::shape_calculator::compute_conv3d_shape(src0->tensor_shape(), src1->tensor_shape(), conv_info);
117 
118  DataType data_type = src0->data_type();
119 
121  ARM_COMPUTE_RETURN_ERROR_ON(dst->data_type() != data_type);
122  }
123 
124  return Status{};
125 }
126 } // namespace
127 
128 void CpuDirectConv3dKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, ITensorInfo *dst, const Conv3dInfo &conv_info)
129 {
130  ARM_COMPUTE_UNUSED(src2);
131  ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst);
132 
133  const auto *uk = CpuDirectConv3dKernel::get_implementation(DataTypeISASelectorData{ src0->data_type(), CPUInfo::get().get_isa() });
134 
136 
137  _conv_info = conv_info;
138  _run_method = uk->ukernel;
139  _name = std::string("CpuDirectConv3dKernel").append("/").append(uk->name);
140 
141  // Get convolved dimensions
143 
144  DataType data_type = src0->data_type();
145 
146  // Output auto inizialitation if not yet initialized
147  auto_init_if_empty(*dst, output_shape, 1, data_type);
148 
149  // Perform validation step
150  ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src0, src1, src2, dst, conv_info));
151 
152  // Configure kernel window
153  Window win = calculate_max_window(*dst, Steps());
155 }
156 
157 Status CpuDirectConv3dKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info)
158 {
159  ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src0, src1, src2, dst, conv_info));
160 
161  return Status{};
162 }
163 
164 void CpuDirectConv3dKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
165 {
166  ARM_COMPUTE_UNUSED(info);
168  ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window);
169  ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
170 
171  auto src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
172  auto src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
173  auto src2 = tensors.get_const_tensor(TensorType::ACL_SRC_2);
174  auto dst = tensors.get_tensor(TensorType::ACL_DST);
175 
176  _run_method(src0, src1, src2, dst, _conv_info, window);
177 }
178 
179 const char *CpuDirectConv3dKernel::name() const
180 {
181  return _name.c_str();
182 }
183 
184 const std::vector<CpuDirectConv3dKernel::DirectConv3dKernel> &CpuDirectConv3dKernel::get_available_kernels()
185 {
186  return available_kernels;
187 }
188 
189 } // namespace kernels
190 } // namespace cpu
191 } // namespace arm_compute
bool is_data_type_quantized(DataType dt)
Check if a given data type is of quantized type.
Definition: Utils.h:1030
Window calculate_max_window(const ValidRegion &valid_region, const Steps &steps, bool skip_border, BorderSize border_size)
Status validate(const OperatorGraph &op_graph)
Return the validity of op_graph, usually after performing an operation (e.g.
Shape of a tensor.
Definition: TensorShape.h:39
Descriptor used by the 3d Convolution function.
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(...)
Definition: Validate.h:490
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:115
#define REGISTER_FP16_NEON(func_name)
Definition: Registrars.h:48
#define REGISTER_FP32_NEON(func_name)
Definition: Registrars.h:74
#define ARM_COMPUTE_RETURN_ON_ERROR(status)
Checks if a status contains an error and returns it.
Definition: Error.h:204
virtual DataType data_type() const =0
Data type used for each element of the tensor.
1 channel, 1 F32 per channel
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
#define REGISTER_QASYMM8_SIGNED_NEON(func_name)
Definition: Registrars.h:96
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
#define ARM_COMPUTE_ERROR_THROW_ON(status)
Definition: Error.h:455
Status class.
Definition: Error.h:52
Status validate_arguments(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *dst, const PadStrideInfo &conv_info)
#define ARM_COMPUTE_RETURN_ERROR_ON(cond)
If the condition is true, an error is returned.
Definition: Error.h:296
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(...)
Definition: Validate.h:284
Copyright (c) 2017-2022 Arm Limited.
1 channel, 1 F16 per channel
#define ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(...)
Definition: Validate.h:159
1 channel, 1 S32 per channel
const ITensor * get_const_tensor(int id) const
Get constant tensor of a given id.
Definition: ITensorPack.cpp:54
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
#define REGISTER_QASYMM8_NEON(func_name)
Definition: Registrars.h:117
virtual const TensorShape & tensor_shape() const =0
Size for each dimension of the tensor.
quantized, asymmetric fixed-point 8-bit number unsigned
Class to describe a number of elements in each dimension.
Definition: Steps.h:40
bool auto_init_if_empty(ITensorInfo &info, const TensorShape &shape, int num_channels, DataType data_type, QuantizationInfo quantization_info=QuantizationInfo())
Auto initialize the tensor info (shape, number of channels and data type) if the current assignment i...
const char * name
Num samples, depth, height, width, channels.
#define ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(k)
Definition: Validate.h:915
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
ITensor * get_tensor(int id)
Get tensor of a given id from the pac.
Definition: ITensorPack.cpp:64
Information about executing thread and CPU.
Definition: CPPTypes.h:179
TensorShape compute_conv3d_shape(const TensorShape &src, const TensorShape &weights, const Conv3dInfo &conv3d_info)
Calculate the output shape of 3d Convolution.
size_t get_data_layout_dimension_index(const DataLayout &data_layout, const DataLayoutDimension &data_layout_dimension)
Get the index of the given dimension.
Definition: Helpers.inl:193
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:541
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:788
#define ARM_COMPUTE_RETURN_ERROR_ON_MSG(cond, msg)
If the condition is true, an error is returned.
Definition: Error.h:244
Tensor packing service.
Definition: ITensorPack.h:39
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:157
quantized, asymmetric fixed-point 8-bit number signed
Includes all wrapper headers at once.
static CPUInfo & get()
Access the KernelLibrary singleton.
Definition: CPPTypes.cpp:40
im2col_func configure(src_target.info(), dst_target.info(), spatial_kernel, conv_info, has_bias)
DataType
Available data types.
Definition: Types.h:79
DataLayout
[DataLayout enum definition]
Definition: Types.h:113
Describe a multidimensional execution window.
Definition: Window.h:39
#define ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(f, s)
Definition: Validate.h:201
cpuinfo::CpuIsaInfo get_isa() const
Gets the current cpu&#39;s ISA information.
Definition: CPPTypes.cpp:124