Compute Library
 21.11
CpuDirectConv3dKernel.cpp
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1 /*
2  * Copyright (c) 2021 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
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25 
26 #include "arm_compute/core/Error.h"
30 #include "arm_compute/core/Types.h"
31 #include "arm_compute/core/Utils.h"
34 #include "src/core/CPP/Validate.h"
39 
40 #include <algorithm>
41 
42 using namespace arm_compute::detail;
43 
44 namespace arm_compute
45 {
46 namespace cpu
47 {
48 namespace kernels
49 {
50 namespace
51 {
52 struct DirectConv3dSelectorData
53 {
55  const CPUInfo &ci;
56 };
59 struct DirectConv3dKernel
60 {
61  const char *name;
62  const DirectConv3dSelectorPtr is_selected;
63  DirectConv3dKernelPtr ukernel;
64 };
65 
66 static const DirectConv3dKernel available_kernels[] =
67 {
68 #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
69  {
70  "neon_fp16_directconv3d",
71  [](const DirectConv3dSelectorData & data) { return data.dt == DataType::F16 && data.ci.has_fp16(); },
72  REGISTER_FP16_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float16_t>)
73  },
74 #endif /* !defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) */
75  {
76  "neon_fp32_directconv3d",
77  [](const DirectConv3dSelectorData & data) { return data.dt == DataType::F32; },
78  REGISTER_FP32_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float>)
79  },
80  {
81  "neon_qasymm8_directconv3d",
82  [](const DirectConv3dSelectorData & data) { return data.dt == DataType::QASYMM8; },
83  REGISTER_QASYMM8_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<uint8_t>)
84  },
85  {
86  "neon_qasymm8_signed_directconv3d",
87  [](const DirectConv3dSelectorData & data) { return data.dt == DataType::QASYMM8_SIGNED; },
88  REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<int8_t>)
89  }
90 };
91 
92 /** Micro-kernel selector
93  *
94  * @param[in] data Selection data passed to help pick the appropriate micro-kernel
95  *
96  * @return A matching micro-kernel else nullptr
97  */
98 const DirectConv3dKernel *get_implementation(const DirectConv3dSelectorData &data)
99 {
100  for(const auto &uk : available_kernels)
101  {
102  if(uk.is_selected(data))
103  {
104  return &uk;
105  }
106  }
107  return nullptr;
108 }
109 
110 Status validate_arguments(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv_info)
111 {
112  ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst);
113  ARM_COMPUTE_RETURN_ERROR_ON(src0->data_layout() != DataLayout::NDHWC);
118  ARM_COMPUTE_RETURN_ERROR_ON(conv_info.dilation != Size3D(1U, 1U, 1U));
119 
120  const auto *uk = get_implementation(DirectConv3dSelectorData{ src0->data_type(), CPUInfo::get() });
121  ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
122 
123  const DataLayout data_layout = src0->data_layout();
124  const int channel_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::CHANNEL);
125 
126  // Weight layout is D, H, W, Cin, Cout
127  ARM_COMPUTE_RETURN_ERROR_ON(src1->num_dimensions() > 5);
128  ARM_COMPUTE_RETURN_ERROR_ON(src1->dimension(1) != src0->dimension(channel_idx));
129 
130  if(src2 != nullptr)
131  {
132  if(is_data_type_quantized(src0->data_type()))
133  {
135  }
136  else
137  {
139  }
140  ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->dimension(0) != src1->dimension(0), "Biases size and number of dst feature maps should match");
141  ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->num_dimensions() > 1, "Biases should be one dimensional");
142  }
143 
144  // Checks performed when output is configured
145  if(dst->total_size() != 0)
146  {
147  TensorShape output_shape = misc::shape_calculator::compute_conv3d_shape(src0->tensor_shape(), src1->tensor_shape(), conv_info);
148 
149  DataType data_type = src0->data_type();
150 
152  ARM_COMPUTE_RETURN_ERROR_ON(dst->data_type() != data_type);
153  }
154 
155  return Status{};
156 }
157 } // namespace
158 
160 {
161  ARM_COMPUTE_UNUSED(src2);
162  ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst);
163 
164  const auto *uk = get_implementation(DirectConv3dSelectorData{ src0->data_type(), CPUInfo::get() });
166 
167  _conv_info = conv_info;
168  _run_method = uk->ukernel;
169  _name = std::string("CpuDirectConv3dKernel").append("/").append(uk->name);
170 
171  // Get convolved dimensions
173 
174  DataType data_type = src0->data_type();
175 
176  // Output auto inizialitation if not yet initialized
177  auto_init_if_empty(*dst, output_shape, 1, data_type);
178 
179  // Perform validation step
180  ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(src0, src1, src2, dst, conv_info));
181 
182  // Configure kernel window
183  Window win = calculate_max_window(*dst, Steps());
185 }
186 
188 {
189  ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(src0, src1, src2, dst, conv_info));
190 
191  return Status{};
192 }
193 
194 void CpuDirectConv3dKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
195 {
196  ARM_COMPUTE_UNUSED(info);
198  ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window);
199  ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
200 
201  auto src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
202  auto src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
203  auto src2 = tensors.get_const_tensor(TensorType::ACL_SRC_2);
204  auto dst = tensors.get_tensor(TensorType::ACL_DST);
205 
206  _run_method(src0, src1, src2, dst, _conv_info, window);
207 }
208 
209 const char *CpuDirectConv3dKernel::name() const
210 {
211  return _name.c_str();
212 }
213 } // namespace kernels
214 } // namespace cpu
215 } // namespace arm_compute
bool is_data_type_quantized(DataType dt)
Check if a given data type is of quantized type.
Definition: Utils.h:981
Window calculate_max_window(const ValidRegion &valid_region, const Steps &steps, bool skip_border, BorderSize border_size)
Shape of a tensor.
Definition: TensorShape.h:39
Descriptor used by the 3d Convolution function.
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(...)
Definition: Validate.h:490
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:115
#define REGISTER_FP16_NEON(func_name)
Definition: Registrars.h:42
#define REGISTER_FP32_NEON(func_name)
Definition: Registrars.h:61
#define ARM_COMPUTE_RETURN_ON_ERROR(status)
Checks if a status contains an error and returns it.
Definition: Error.h:204
virtual DataType data_type() const =0
Data type used for each element of the tensor.
1 channel, 1 F32 per channel
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
#define REGISTER_QASYMM8_SIGNED_NEON(func_name)
Definition: Registrars.h:76
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
#define ARM_COMPUTE_ERROR_THROW_ON(status)
Definition: Error.h:455
Status class.
Definition: Error.h:52
#define ARM_COMPUTE_RETURN_ERROR_ON(cond)
If the condition is true, an error is returned.
Definition: Error.h:296
decltype(strategy::transforms) typedef type
const CPUInfo & ci
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(...)
Definition: Validate.h:284
Copyright (c) 2017-2021 Arm Limited.
1 channel, 1 F16 per channel
#define ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(...)
Definition: Validate.h:159
1 channel, 1 S32 per channel
const DataType data_type
Definition: Im2Col.cpp:150
const ITensor * get_const_tensor(int id) const
Get constant tensor of a given id.
Definition: ITensorPack.cpp:54
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
#define REGISTER_QASYMM8_NEON(func_name)
Definition: Registrars.h:90
virtual const TensorShape & tensor_shape() const =0
Size for each dimension of the tensor.
quantized, asymmetric fixed-point 8-bit number unsigned
Class to describe a number of elements in each dimension.
Definition: Steps.h:40
bool auto_init_if_empty(ITensorInfo &info, const TensorShape &shape, int num_channels, DataType data_type, QuantizationInfo quantization_info=QuantizationInfo())
Auto initialize the tensor info (shape, number of channels and data type) if the current assignment i...
Num samples, depth, height, width, channels.
#define ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(k)
Definition: Validate.h:915
const char * name
DataType dt
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
ITensor * get_tensor(int id)
Get tensor of a given id from the pac.
Definition: ITensorPack.cpp:64
Information about executing thread and CPU.
Definition: CPPTypes.h:158
TensorShape compute_conv3d_shape(const TensorShape &src, const TensorShape &weights, const Conv3dInfo &conv3d_info)
Calculate the output shape of 3d Convolution.
size_t get_data_layout_dimension_index(const DataLayout &data_layout, const DataLayoutDimension &data_layout_dimension)
Get the index of the given dimension.
Definition: Helpers.inl:193
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:541
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:788
const DirectConv3dSelectorPtr is_selected
#define ARM_COMPUTE_RETURN_ERROR_ON_MSG(cond, msg)
If the condition is true, an error is returned.
Definition: Error.h:244
Tensor packing service.
Definition: ITensorPack.h:39
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:157
quantized, asymmetric fixed-point 8-bit number signed
Includes all wrapper headers at once.
static CPUInfo & get()
Access the KernelLibrary singleton.
Definition: CPPTypes.cpp:39
im2col_func configure(src_target.info(), dst_target.info(), spatial_kernel, conv_info, has_bias)
DataType
Available data types.
Definition: Types.h:79
DataLayout
[DataLayout enum definition]
Definition: Types.h:113
DirectConv3dKernelPtr ukernel
Describe a multidimensional execution window.
Definition: Window.h:39
#define ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(f, s)
Definition: Validate.h:201
Status validate(const ITensorInfo *scores_in, const ITensorInfo *boxes_in, const ITensorInfo *batch_splits_in, const ITensorInfo *scores_out, const ITensorInfo *boxes_out, const ITensorInfo *classes, const ITensorInfo *batch_splits_out, const ITensorInfo *keeps, const ITensorInfo *keeps_size, const BoxNMSLimitInfo info)