Compute Library
 21.08
CpuGemmAssemblyDispatch.cpp
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25 
27 #include "src/core/CPP/Validate.h"
33 
34 #include <arm_neon.h>
35 
36 namespace arm_compute
37 {
38 namespace cpu
39 {
40 using namespace arm_compute::experimental;
41 
42 namespace
43 {
44 struct free_delete
45 {
46  void operator()(void *x)
47  {
48  free(x);
49  }
50 };
51 
52 struct Params
53 {
54  unsigned int M;
55  unsigned int N;
56  unsigned int K;
57  unsigned int batches;
58  unsigned int multis;
59  unsigned int sections;
60  bool indirect;
61 };
62 
63 Params extract_parameters(const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *d, const AsmGemmInfo &info)
64 {
66  Params p;
67  p.M = d->tensor_shape().y();
68  p.K = a->tensor_shape().x();
69  p.N = d->tensor_shape().x();
70  p.batches = 1;
71  p.multis = 1;
72  p.sections = 1;
73  p.indirect = false;
74 
75  if(info.method == AsmConvMethod::Conv || info.method == AsmConvMethod::Indirect)
76  {
77  p.indirect = true;
78  p.sections = b->tensor_shape()[2] * b->tensor_shape()[3];
79  }
80  else
81  {
82  p.multis = b->tensor_shape().z();
83  p.batches = d->tensor_shape().total_size_upper(2) / p.multis;
84  }
85 
86  // Update M in case of GEMM3D for output
87  if(info.depth_output_gemm3d != 0)
88  {
89  p.M = d->tensor_shape().y() * d->tensor_shape().z();
90  p.batches = d->tensor_shape().total_size_upper(3) / p.multis;
91  }
92 
93  return p;
94 }
95 
96 IScheduler::Hints scheduling_hint_heuristic(arm_gemm::GemmMethod method, DataType data_type)
97 {
98  // Schedule assembly kernel
99  const int granule_threshold = 200;
100  IScheduler::Hints scheduling_hint = IScheduler::Hints(Window::DimX);
101  if(method == arm_gemm::GemmMethod::GEMM_INTERLEAVED && data_type == DataType::F32)
102  {
103  scheduling_hint = IScheduler::Hints(Window::DimX, IScheduler::StrategyHint::DYNAMIC, granule_threshold);
104  }
105  else if(method == arm_gemm::GemmMethod::GEMM_INTERLEAVED_2D && (data_type == DataType::F32 || data_type == DataType::F16 || data_type == DataType::U8 || data_type == DataType::S8))
106  {
107  //GEMM_INTERLEAVED supports 2D parallelism, IScheduler::split_dimensions_all signals to parallelise over all window dimensions
108  scheduling_hint = IScheduler::Hints(IScheduler::split_dimensions_all, IScheduler::StrategyHint::STATIC, granule_threshold);
109  }
110  else if(method == arm_gemm::GemmMethod::QUANTIZE_WRAPPER_2D && (data_type == DataType::QASYMM8 || data_type == DataType::QASYMM8_SIGNED))
111  {
112  //special case for QASYMM8 to support 2D parallelism, scheduler here may be tweaked differently compared to FP32 case
113  scheduling_hint = IScheduler::Hints(IScheduler::split_dimensions_all, IScheduler::StrategyHint::STATIC, granule_threshold);
114  }
115 
116  return scheduling_hint;
117 }
118 
119 /** Fallback in case ACL doesn't have a function */
120 template <typename TypeInput, typename TypeOutput, class OutputStage = arm_gemm::Nothing>
121 class Fallback : public CpuGemmAssemblyDispatch::IFallback
122 {
123 public:
124  /** Destructor */
125  ~Fallback() = default;
126 
127  /** Initialise the functions's input and output.
128  *
129  * @param[in] a Input tensor containing the Matrix A.
130  * @param[in] b Input tensor containing the Matrix B.
131  * @param[in] c Input tensor containing the Matrix C.
132  * @param[out] d Output tensor to store the result of matrix multiplication.
133  * @param[in] args Matrix multiplication information.
134  * @param[in] gemm_info GEMM meta-data
135  * @param[in] os Output stage meta-data.
136  */
137  void configure(const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *c, ITensorInfo *d,
138  arm_gemm::GemmArgs args, const AsmGemmInfo &gemm_info,
139  const OutputStage &os = {});
140 
141  /** Set requantization shifts to be used
142  *
143  * @param[in] shifts Requantization shifts
144  *
145  * @return Pointer to the shift data
146  */
147  /** Set requantization data to be used
148  *
149  *
150  * @param shifts Requantization shifts
151  * @param multipliers Requantization multipliers
152  *
153  * @return A tuple with the pointers to the shift and multiplier data respectively
154  */
155  std::tuple<bool, const int32_t *, const int32_t *, const int32_t *> set_requantize_data(const std::vector<int32_t> &shifts,
156  const std::vector<int32_t> &multipliers);
157 
158  // Inherited methods overridden:
159  void run(ITensorPack &tensors) override;
160  void prepare(ITensorPack &tensors) override;
161  bool is_configured() const override;
162  experimental::MemoryRequirements workspace() const override;
163 
164 private:
165  enum AuxTensorIdx
166  {
167  AsmGemmWorkspace = 0,
168  Pretranspose,
169  Count
170  };
171 
172  /** Configure the indirect buffer
173  *
174  * @param[in] a Input tensor containing the Matrix A.
175  * @param[in] b Input tensor containing the Matrix B.
176  * @param[out] d Output tensor to store the result of matrix multiplication.
177  * @param[in] info GEMM meta-data
178  */
179  void configure_indirect(const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *d, const AsmGemmInfo &info);
180  /** Prepare the indirect buffer */
181  void prepare_indirect_buffer(ITensorPack &tensors);
182 
183  /** Assembly Gemm kernel */
184  std::shared_ptr<arm_gemm::GemmCommon<TypeInput, TypeOutput>> _gemm_kernel_asm{ nullptr };
185  /** Optimised Arm® Neon™ kernel */
186  std::unique_ptr<INEKernel> _optimised_kernel{ nullptr };
187  /** Assembly GEMM workspace tensor info */
188  TensorInfo _workspace_info{};
189  /** Pre-transpose tensor info */
190  TensorInfo _pretranspose_info{};
191  /** Prepared flag */
192  bool _is_prepared{ false };
193  /** GEMM meta-data */
194  AsmGemmInfo _gemm_info{};
195  /** GEMM kernel description */
196  arm_gemm::KernelDescription _kernel_info{};
197  /** Per channel quantization shifts */
198  std::vector<int32_t> _shifts{};
199  std::vector<int32_t> right_shifts{};
200  std::vector<int32_t> left_shifts{};
201  /** Per channel quantization multipliers */
202  std::vector<int32_t> _multipliers{};
203  /** Indirect buffer */
204  std::unique_ptr<const TypeInput *const *, free_delete> _indirect_arg{};
205  std::unique_ptr<const TypeInput *, free_delete> _indirect_buf{};
206  std::vector<TypeInput> _indirect_pad{};
208  experimental::MemoryRequirements _aux_mem{ Count };
209 };
210 
211 template <typename TypeInput, typename TypeOutput, class OutputStage>
212 std::tuple<bool, const int32_t *, const int32_t *, const int32_t *>
213 Fallback<TypeInput, TypeOutput, OutputStage>::set_requantize_data(const std::vector<int32_t> &shifts, const std::vector<int32_t> &multipliers)
214 {
215  _multipliers = multipliers;
216  _shifts = shifts;
217  bool need_left = false;
218  for(const auto s : _shifts)
219  {
220  left_shifts.push_back(std::max(-s, int32_t(0)));
221  right_shifts.push_back(std::min(-s, int32_t(0)));
222  if(s < 0 && !need_left)
223  {
224  need_left = true;
225  }
226  }
227  return std::make_tuple(need_left, left_shifts.data(), right_shifts.data(), _multipliers.data());
228 }
229 
230 template <typename TypeInput, typename TypeOutput, class OutputStage>
231 void Fallback<TypeInput, TypeOutput, OutputStage>::prepare_indirect_buffer(ITensorPack &tensors)
232 {
233  auto a = tensors.get_const_tensor(TensorType::ACL_SRC_0);
234  const TypeInput *A_ptr = reinterpret_cast<TypeInput *>(a->buffer());
235  const int multis = 1;
236  const int batches = a->info()->tensor_shape().total_size_upper(3);
237  const size_t stride_A = a->info()->strides_in_bytes().y() / sizeof(TypeInput);
238  const size_t batch_stride_A = a->info()->strides_in_bytes()[3] / sizeof(TypeInput);
239  const size_t multi_stride_A = a->info()->strides_in_bytes()[4] / sizeof(TypeInput);
240 
241  const size_t output_hw = _cp.output_height * _cp.output_width;
242  const int batch_size = _cp.kernel_height * _cp.kernel_width * output_hw * sizeof(TypeInput);
243  const size_t batch_stride = batch_size / sizeof(TypeInput);
244  const int multi_size = batch_size * batches;
245  const size_t multi_stride = multi_size / sizeof(TypeInput);
246 
247  for(int64_t m = 0; m < multis; m++)
248  {
249  for(int64_t b = 0; b < batches; b++)
250  {
251  for(int64_t output_y = 0; output_y < _cp.output_height; output_y++)
252  {
253  for(int64_t output_x = 0; output_x < _cp.output_width; output_x++)
254  {
255  int64_t output_xy = (output_y * _cp.output_width) + output_x;
256 
257  for(int64_t kernel_y = 0; kernel_y < _cp.kernel_height; kernel_y++)
258  {
259  for(int64_t kernel_x = 0; kernel_x < _cp.kernel_width; kernel_x++)
260  {
261  int64_t input_x = (output_x * _cp.output_stride_w) + kernel_x - _cp.padding_left;
262  int64_t input_y = (output_y * _cp.output_stride_h) + kernel_y - _cp.padding_top;
263  int64_t kernel_xy = (kernel_y * _cp.kernel_width) + kernel_x;
264  int64_t input_xy = (input_y * _cp.input_width) + input_x;
265 
266  if(input_x < 0 || input_x >= _cp.input_width || input_y < 0 || input_y >= _cp.input_height)
267  {
268  _indirect_buf.get()[m * multi_stride + b * batch_stride + kernel_xy * output_hw + output_xy] = _indirect_pad.data();
269  }
270  else
271  {
272  _indirect_buf.get()[m * multi_stride + b * batch_stride + kernel_xy * output_hw + output_xy] =
273  A_ptr + (m * multi_stride_A + b * batch_stride_A + input_xy * stride_A);
274  }
275  }
276  }
277  }
278  }
279  }
280  }
281 }
282 
283 template <typename TypeInput, typename TypeOutput, class OutputStage>
284 void Fallback<TypeInput, TypeOutput, OutputStage>::configure_indirect(const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *d, const AsmGemmInfo &info)
285 {
286  ARM_COMPUTE_ERROR_ON(!(info.method == AsmConvMethod::Conv || info.method == AsmConvMethod::Indirect));
287 
288  float zeropad = 0.f;
289  if(is_data_type_quantized(a->data_type()))
290  {
291  zeropad = a->quantization_info().uniform().offset;
292  }
293 
294  const int64_t input_width = static_cast<int64_t>(a->tensor_shape()[1]);
295  const int64_t input_height = static_cast<int64_t>(a->tensor_shape()[2]);
296  const int64_t input_channels = static_cast<int64_t>(a->tensor_shape()[0]);
297  const int64_t kernel_width = static_cast<int64_t>(b->tensor_shape()[2]);
298  const int64_t kernel_height = static_cast<int64_t>(b->tensor_shape()[3]);
299  const int64_t output_width = static_cast<int64_t>(d->tensor_shape()[1]);
300  const int64_t output_height = static_cast<int64_t>(d->tensor_shape()[2]);
301 
302  _cp = { input_width, input_height, input_channels, kernel_width, kernel_height, output_width, output_height,
303  info.ps_info.stride().first, info.ps_info.stride().second, info.padding_top, info.padding_left, zeropad
304  };
305 
306  if(info.method == AsmConvMethod::Conv)
307  {
308  _gemm_kernel_asm->set_convolution_parameters(_cp);
309  }
310 
311  if(info.method == AsmConvMethod::Indirect)
312  {
313  const unsigned int multis = 1;
314  const unsigned int batches = a->tensor_shape().total_size_upper(3);
315  const unsigned int kernel_hw = _cp.kernel_width * _cp.kernel_height;
316  const unsigned int output_hw = _cp.output_width * _cp.output_height;
317 
318  using TypeInputPtr = TypeInput *;
319  const int batch_size = kernel_hw * output_hw * sizeof(TypeInputPtr);
320  const size_t batch_stride = batch_size / sizeof(TypeInputPtr);
321  const int multi_size = batch_size * batches;
322  const size_t multi_stride = multi_size / sizeof(TypeInputPtr);
323 
324  _indirect_buf = std::unique_ptr<const TypeInput *, free_delete>(reinterpret_cast<const TypeInput **>(malloc(multi_size * multis)));
325  _indirect_arg = std::unique_ptr<const TypeInput *const *, free_delete>(reinterpret_cast<const TypeInput *const **>(malloc(sizeof(TypeInput **) * kernel_hw * multis * batches)));
326  _indirect_pad = std::vector<TypeInput>(_cp.input_channels, TypeInput(zeropad));
327 
328  // Set indirect argument
329  int64_t pos = 0;
330  for(int64_t m = 0; m < multis; m++)
331  {
332  for(int64_t b = 0; b < batches; b++)
333  {
334  for(int64_t kernel_xy = 0; kernel_xy < kernel_hw; kernel_xy++)
335  {
336  (_indirect_arg.get())[pos++] = _indirect_buf.get() + m * multi_stride + b * batch_stride + kernel_xy * output_hw;
337  }
338  }
339  }
340 
341  _gemm_kernel_asm->set_indirect_parameters(a->tensor_shape()[0], _indirect_arg.get());
342  }
343 }
344 
345 template <typename TypeInput, typename TypeOutput, class OutputStage>
346 void Fallback<TypeInput, TypeOutput, OutputStage>::configure(const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *c, ITensorInfo *d,
347  arm_gemm::GemmArgs args, const AsmGemmInfo &gemm_info,
348  const OutputStage &os)
349 {
351  arm_gemm::GemmConfig gemm_cfg;
352  _kernel_info = arm_gemm::get_gemm_method<TypeInput, TypeOutput, OutputStage>(args, os);
353  if(_kernel_info.method != arm_gemm::GemmMethod::GEMV_BATCHED)
354  {
355  gemm_cfg.filter = _kernel_info.name;
356  args._cfg = &gemm_cfg;
357  }
358  _gemm_kernel_asm = arm_gemm::gemm<TypeInput, TypeOutput, OutputStage>(args, os);
359  if(_gemm_kernel_asm == nullptr)
360  {
361  //configuration not supported: Leave function unconfigured:
362  return;
363  }
364 
365  // arm_compute wrapper for the Gemm object (see above)
366  auto acl_gemm_wrapper = std::make_unique<kernel::CpuGemmAssemblyWrapperKernel<TypeInput, TypeOutput>>();
367  ARM_COMPUTE_ERROR_ON(acl_gemm_wrapper == nullptr);
368  acl_gemm_wrapper->configure(_gemm_kernel_asm.get(), gemm_cfg.filter);
369  const size_t workspace_size = _gemm_kernel_asm->get_working_size();
370  const unsigned int alignment = 4096;
371  _workspace_info = TensorInfo(TensorShape(workspace_size), 1, DataType::U8);
372  _aux_mem[AsmGemmWorkspace] = MemoryInfo(offset_int_vec(AsmGemmWorkspace), MemoryLifetime::Temporary, workspace_size, alignment);
373 
374  //if we disable this code below in brackets then ConvLayer deadlocks when threads > 1 and
375  //the shapes are In=1x1x1024 Weights=1x1x1024x1001 Biases=1001 Out=1x1x1001
376  {
377  const unsigned int window_size = _gemm_kernel_asm->get_window_size().total_size();
378  if(window_size < static_cast<unsigned int>(args._maxthreads))
379  {
380  _gemm_kernel_asm->set_nthreads(window_size);
381  }
382  }
383 
384  _optimised_kernel = std::move(acl_gemm_wrapper);
385  _gemm_info = gemm_info;
386  // Check for pre-transposed support
387  if(_gemm_kernel_asm->B_pretranspose_required())
388  {
389  // Forcing 128-byte alignment (required by 32-bit kernels)
390  const unsigned int alignment = 128;
391  const size_t B_pretranspose_size = _gemm_kernel_asm->get_B_pretransposed_array_size();
392  _pretranspose_info = TensorInfo(TensorShape(B_pretranspose_size), 1, DataType::U8);
393  _aux_mem[Pretranspose] = MemoryInfo(offset_int_vec(Pretranspose), MemoryLifetime::Persistent, B_pretranspose_size, alignment);
394  }
395 
396  // Handle indirect GEMM convolution
397  if(gemm_info.method == AsmConvMethod::Conv || gemm_info.method == AsmConvMethod::Indirect)
398  {
399  configure_indirect(a, b, d, gemm_info);
400  }
401 }
402 
403 template <typename TypeInput, typename TypeOutput, class OutputStage>
404 void Fallback<TypeInput, TypeOutput, OutputStage>::prepare(ITensorPack &tensors)
405 {
406  if(!_is_prepared)
407  {
408  auto b = tensors.get_const_tensor(TensorType::ACL_SRC_1);
409  auto c = tensors.get_const_tensor(TensorType::ACL_SRC_2);
410 
411  // Setup up matrix bias in the assembly kernel, it's just a pointer to matrix C.
412  if(c && c->info()->data_type() == DataType::S32)
413  {
414  _gemm_kernel_asm->set_quantized_bias(reinterpret_cast<const int32_t *>(c->buffer() + c->info()->offset_first_element_in_bytes()), 0);
415  }
416 
417  // Pretranspose B if required
418  if(_gemm_kernel_asm->B_pretranspose_required())
419  {
420  const int ldb = b->info()->strides_in_bytes().y() / sizeof(TypeInput);
421  const auto in1_ptr = reinterpret_cast<const TypeInput *>(b->buffer() + b->info()->offset_first_element_in_bytes());
422  const int multi_stride_b = b->info()->strides_in_bytes().z() / sizeof(TypeInput);
423 
424  CpuAuxTensorHandler pretranspose(offset_int_vec(Pretranspose), _pretranspose_info, tensors, false);
425  ARM_COMPUTE_ERROR_ON(pretranspose.get()->buffer() == nullptr);
426  _gemm_kernel_asm->pretranspose_B_array(pretranspose.get()->buffer(), in1_ptr, ldb, multi_stride_b);
427 
428  b->mark_as_unused();
429  }
430 
431  if(_gemm_info.method == AsmConvMethod::Indirect)
432  {
433  prepare_indirect_buffer(tensors);
434  }
435 
436  _is_prepared = true;
437  }
438 }
439 
440 template <typename TypeInput, typename TypeOutput, class OutputStage>
441 bool Fallback<TypeInput, TypeOutput, OutputStage>::is_configured() const
442 {
443  return _optimised_kernel != nullptr;
444 }
445 
446 template <typename TypeInput, typename TypeOutput, class OutputStage>
447 experimental::MemoryRequirements Fallback<TypeInput, TypeOutput, OutputStage>::workspace() const
448 {
449  return _aux_mem;
450 }
451 
452 template <typename TypeInput, typename TypeOutput, class OutputStage>
453 void Fallback<TypeInput, TypeOutput, OutputStage>::run(ITensorPack &tensors)
454 {
455  auto a = tensors.get_const_tensor(TensorType::ACL_SRC_0);
456  auto b = tensors.get_const_tensor(TensorType::ACL_SRC_1);
457  auto c = tensors.get_const_tensor(TensorType::ACL_SRC_2);
458  auto d = tensors.get_tensor(TensorType::ACL_DST);
459 
460  int lda = a->info()->strides_in_bytes().y() / sizeof(TypeInput);
461  int ldb = 0;
462  const int ldd = d->info()->strides_in_bytes().y() / sizeof(TypeOutput);
463 
464  const size_t a_batch_idx = _gemm_info.reinterpret_input_as_3d != 0 ? 3 : 2;
465  const size_t a_multi_idx = a_batch_idx + 1;
466  const size_t d_batch_idx = _gemm_info.depth_output_gemm3d != 0 ? 3 : 2;
467  const size_t d_multi_idx = d_batch_idx + 1;
468 
469  int batch_stride_a = a->info()->strides_in_bytes()[a_batch_idx] / sizeof(TypeInput);
470  const int batch_stride_d = d->info()->strides_in_bytes()[d_batch_idx] / sizeof(TypeOutput);
471 
472  int multi_stride_a = a->info()->strides_in_bytes()[a_multi_idx] / sizeof(TypeInput);
473  int multi_stride_b = 0;
474  const int multi_stride_d = d->info()->strides_in_bytes()[d_multi_idx] / sizeof(TypeOutput);
475 
476  auto in0_ptr = reinterpret_cast<const TypeInput *>(a->buffer() + a->info()->offset_first_element_in_bytes());
477  const TypeInput *in1_ptr = nullptr;
478  auto out_ptr = reinterpret_cast<TypeOutput *>(d->buffer() + d->info()->offset_first_element_in_bytes());
479 
480  // Check if B is pre-tranposed and de-reference if not
481  if(!_gemm_kernel_asm->B_is_pretransposed())
482  {
483  ldb = b->info()->strides_in_bytes().y() / sizeof(TypeInput);
484  multi_stride_b = b->info()->strides_in_bytes().z() / sizeof(TypeInput);
485  in1_ptr = reinterpret_cast<const TypeInput *>(b->buffer() + b->info()->offset_first_element_in_bytes());
486  }
487 
488  const auto scheduling_hint = scheduling_hint_heuristic(_kernel_info.method, d->info()->data_type());
489 
490  // Set workspace if needed and reset number of threads as buffer manager gets re-created with max_threads
491  CpuAuxTensorHandler workspace(offset_int_vec(AsmGemmWorkspace), _workspace_info, tensors, false);
492  if(workspace.get()->buffer() != nullptr)
493  {
494  _gemm_kernel_asm->set_working_space(reinterpret_cast<void *>(workspace.get()->buffer()));
495  const unsigned int split_dim = scheduling_hint.split_dimension();
496  const unsigned int window_size = _gemm_kernel_asm->get_window_size().total_size();
497  unsigned int num_threads = NEScheduler::get().num_threads();
498  if(window_size < num_threads)
499  {
500  num_threads = window_size;
501  }
502  if(split_dim != IScheduler::split_dimensions_all)
503  {
504  // Make sure the kernel does not expect more threads than we can actually spawn
505  const unsigned int num_iterations = _optimised_kernel.get()->window().num_iterations(split_dim);
506  num_threads = std::min(num_iterations, num_threads);
507  }
508  _gemm_kernel_asm->set_nthreads(num_threads);
509  }
510 
511  // Prepare assembly kernel
512  prepare(tensors);
513 
514  // Setup up matrix bias in the assembly kernel, it's just a pointer to matrix C.
515  TypeOutput *bias = nullptr;
516  if(c && c->info()->data_type() != DataType::S32)
517  {
518  bias = reinterpret_cast<TypeOutput *>(c->buffer() + c->info()->offset_first_element_in_bytes());
519  }
520 
521  if(_gemm_info.method == AsmConvMethod::Indirect)
522  {
523  in0_ptr = nullptr;
524  lda = 0;
525  batch_stride_a = 0;
526  multi_stride_a = 0;
527  }
528 
529  // Set gemm parameters
530  _gemm_kernel_asm->set_arrays(in0_ptr, lda, batch_stride_a, multi_stride_a,
531  in1_ptr, ldb, multi_stride_b,
532  out_ptr, ldd, batch_stride_d, multi_stride_d,
533  bias, 0);
534  // Schedule
535  NEScheduler::get().schedule(_optimised_kernel.get(), scheduling_hint);
536 }
537 
538 template <typename TypeInput, typename TypeOutput>
539 void create_arm_gemm(std::unique_ptr<CpuGemmAssemblyDispatch::IFallback> &arm_gemm,
540  const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *c, ITensorInfo *d,
541  arm_gemm::Activation activation, const AsmGemmInfo &info)
542 {
543  Params p = extract_parameters(a, b, d, info);
544  const CPUInfo &ci = NEScheduler::get().cpu_info();
545  unsigned int num_threads = NEScheduler::get().num_threads();
546 
547  arm_gemm::GemmArgs args(&ci, p.M, p.N, p.K, p.sections, p.batches, p.multis, p.indirect, activation, num_threads, info.fast_mode);
548 
549  // Create arm_gemm fallback
550  auto fallback = std::make_unique<Fallback<TypeInput, TypeOutput>>();
551  fallback->configure(a, b, c, d, args, info);
552  arm_gemm = std::move(fallback);
553 }
554 
555 template <typename TypeInput, typename TypeOutput>
556 void create_arm_gemm_quant(std::unique_ptr<CpuGemmAssemblyDispatch::IFallback> &arm_gemm,
557  const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *c, ITensorInfo *d,
558  arm_gemm::Activation activation, const AsmGemmInfo &info)
559 {
560  ARM_COMPUTE_UNUSED(activation);
561  Params p = extract_parameters(a, b, d, info);
562  const CPUInfo &ci = NEScheduler::get().cpu_info();
563  const unsigned int num_threads = NEScheduler::get().num_threads();
564 
565  arm_gemm::GemmArgs args(&ci, p.M, p.N, p.K, p.sections, p.batches, p.multis, p.indirect, activation, num_threads, info.fast_mode);
566 
567  // Create arm_gemm fallback
568  auto fallback = std::make_unique<Fallback<TypeInput, TypeOutput, arm_gemm::Requantize32>>();
569 
570  // Configure requantization info
571  const int32_t negation = info.negated_offsets ? 1 : -1;
572  const int32_t a_offset = -a->quantization_info().uniform().offset * negation;
573  const int32_t b_offset = -b->quantization_info().uniform().offset * negation;
574  const GEMMLowpOutputStageInfo os_info = info.output_stage;
575 
576  arm_gemm::Requantize32 gemm_requant_info{};
577  if(os_info.gemmlowp_shifts.size() > 1)
578  {
579  const auto requantize_data = fallback->set_requantize_data(os_info.gemmlowp_shifts, os_info.gemmlowp_multipliers);
580  gemm_requant_info = arm_gemm::Requantize32(nullptr, 0,
581  a_offset, b_offset, os_info.gemmlowp_offset,
582  (std::get<0>(requantize_data)) ? std::get<1>(requantize_data) : nullptr,
583  std::get<2>(requantize_data),
584  std::get<3>(requantize_data),
585  os_info.gemmlowp_min_bound, os_info.gemmlowp_max_bound);
586  }
587  else
588  {
589  gemm_requant_info = arm_gemm::Requantize32(nullptr, 0,
590  a_offset, b_offset, os_info.gemmlowp_offset,
591  -os_info.gemmlowp_shift, os_info.gemmlowp_multiplier,
592  os_info.gemmlowp_min_bound, os_info.gemmlowp_max_bound);
593  }
594 
595  // Configure fallback
596  fallback->configure(a, b, c, d, args, info, gemm_requant_info);
597  arm_gemm = std::move(fallback);
598 }
599 } //namespace
600 
602  : _arm_gemm(nullptr)
603 {
604 }
605 
607 {
608  ARM_COMPUTE_UNUSED(c, info);
612 
613 #ifndef __aarch64__
614  ARM_COMPUTE_RETURN_ERROR_ON_MSG(a->element_size() == 1, "8bit integer types only supported for aarch64");
615 #endif /* __aarch64__ */
621  {
623  }
624  else
625  {
627  }
628  ARM_COMPUTE_RETURN_ERROR_ON_MSG(a->data_type() == DataType::F32 && d->data_type() != DataType::F32, "Only F32 output supported for F32 input");
629  ARM_COMPUTE_RETURN_ERROR_ON_MSG(a->data_type() == DataType::F16 && d->data_type() != DataType::F16, "Only F16 output supported for F16 input");
630  ARM_COMPUTE_RETURN_ERROR_ON_MSG(a->data_type() == DataType::BFLOAT16 && d->data_type() != DataType::F32, "Only F32 output supported for BFLOAT16 input");
631  ARM_COMPUTE_RETURN_ERROR_ON_MSG(a->data_type() == DataType::U8 && d->data_type() != DataType::U32, "Only U32 output supported for U8 input");
632  ARM_COMPUTE_RETURN_ERROR_ON_MSG(a->data_type() == DataType::S8 && d->data_type() != DataType::S32, "Only S32 output supported for S8 input");
633  ARM_COMPUTE_RETURN_ERROR_ON_MSG(a->data_type() == DataType::QASYMM8 && d->data_type() != DataType::QASYMM8, "Only QASYMM8 output supported for QASYMM8 input");
634  return Status{};
635 }
636 
638 {
641 }
642 
644 {
647 
648  //If we don't support a combination of data types, silently return: it is the caller's responsibility to check if configure() was successful via is_configured()
649  if(!CpuGemmAssemblyDispatch::validate(a, b, c, d, info))
650  {
651  return;
652  }
653 
654  switch(a->data_type())
655  {
656  case DataType::F32:
657  create_arm_gemm<float, float>(_arm_gemm, a, b, c, d, act, info);
658  break;
659 #ifdef __aarch64__
660  case DataType::U8:
661  case DataType::QASYMM8:
662  if(d->data_type() == DataType::S32)
663  {
664  create_arm_gemm<uint8_t, uint32_t>(_arm_gemm, a, b, c, d, act, info);
665  }
666  else
667  {
668  create_arm_gemm_quant<uint8_t, uint8_t>(_arm_gemm, a, b, c, d, act, info);
669  }
670  break;
671  case DataType::S8:
673  if(d->data_type() == DataType::S32)
674  {
675  create_arm_gemm<int8_t, int32_t>(_arm_gemm, a, b, c, d, act, info);
676  }
677  else
678  {
679  create_arm_gemm_quant<int8_t, int8_t>(_arm_gemm, a, b, c, d, act, info);
680  }
681  break;
682 #endif /* __aarch64__ */
683 #if defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) || defined(ARM_COMPUTE_FORCE_BF16)
684  case DataType::BFLOAT16:
685  create_arm_gemm<bfloat16, float>(_arm_gemm, a, b, c, d, act, info);
686  break;
687 #endif /* defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) || defined(ARM_COMPUTE_FORCE_BF16) */
688 #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
689  case DataType::F16:
690  create_arm_gemm<float16_t, float16_t>(_arm_gemm, a, b, c, d, act, info);
691  break;
692 #endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
693  default:
694  break;
695  }
696 }
697 
699 {
700  ARM_COMPUTE_ERROR_ON(_arm_gemm == nullptr);
701  _arm_gemm->prepare(tensors);
702 }
703 
705 {
706  return _arm_gemm != nullptr && _arm_gemm->is_configured();
707 }
708 
710 {
711  ARM_COMPUTE_ERROR_ON(_arm_gemm == nullptr);
712  _arm_gemm->run(tensors);
713 }
714 
716 {
717  ARM_COMPUTE_ERROR_ON(_arm_gemm == nullptr);
718  return _arm_gemm->workspace();
719 }
720 } // namespace cpu
721 } // namespace arm_compute
bool is_data_type_quantized(DataType dt)
Check if a given data type is of quantized type.
Definition: Utils.h:981
const CPUInfo & ci
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:115
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_BF16_UNSUPPORTED(tensor)
Definition: Validate.h:121
SimpleTensor< float > b
Definition: DFT.cpp:157
1 channel, 1 U8 per channel
static bool is_activation_supported(const ActivationLayerInfo &activation)
Checks if activation is supported by the gemm assembly dispatcher.
virtual DataType data_type() const =0
Data type used for each element of the tensor.
1 channel, 1 F32 per channel
Split the workload evenly among the threads.
static constexpr unsigned int split_dimensions_all
When arm_compute::ISchedular::Hints::_split_dimension is initialized with this value then the schedul...
Definition: IScheduler.h:62
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
unsigned int M
CPUInfo & cpu_info()
Get CPU info.
Definition: IScheduler.cpp:40
Status class.
Definition: Error.h:52
Activation Layer Information class.
Definition: Types.h:1475
Copyright (c) 2017-2021 Arm Limited.
std::vector< MemoryInfo > MemoryRequirements
Definition: Types.h:113
1 channel, 1 F16 per channel
unsigned int multis
Split the workload dynamically using a bucket system.
#define ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(...)
Definition: Validate.h:159
1 channel, 1 S32 per channel
16-bit brain floating-point number
void run(ITensorPack &tensors) override
Run the kernels contained in the function.
const DataType data_type
Definition: Im2Col.cpp:150
const size_t input_width
static constexpr size_t DimX
Alias for dimension 0 also known as X dimension.
Definition: Window.h:43
static Status validate(const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *c, const ITensorInfo *d, const AsmGemmInfo &info)
Indicates whether or not this function can be used to process the given parameters.
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
1 channel, 1 U32 per channel
bool is_data_type_quantized_per_channel(DataType dt)
Check if a given data type is of per channel type.
Definition: Utils.h:1058
void configure(const ITensorInfo *a, const ITensorInfo *b, const ITensorInfo *c, ITensorInfo *d, const AsmGemmInfo &info)
If supported create a Compute Library function else fallback to the arm_gemm function.
quantized, asymmetric fixed-point 8-bit number unsigned
unsigned int N
virtual size_t element_size() const =0
Element size in bytes calculated as data_size() * num_channels()
bool is_configured() const
Was the function successfully configured ?
void prepare(ITensorPack &tensors) override
Prepare the function for executing.
quantized, symmetric per channel fixed-point 8-bit number
unsigned int sections
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
virtual void schedule(ICPPKernel *kernel, const Hints &hints)=0
Runs the kernel in the same thread as the caller synchronously.
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:541
const size_t input_height
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:788
#define ARM_COMPUTE_RETURN_ERROR_ON_MSG(cond, msg)
If the condition is true, an error is returned.
Definition: Error.h:244
Tensor packing service.
Definition: ITensorPack.h:39
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:157
int offset_int_vec(int offset)
Definition: MemoryHelpers.h:38
std::string filter
Definition: arm_gemm.hpp:69
quantized, asymmetric fixed-point 8-bit number signed
unsigned int batches
arm_gemm::Activation map_to_arm_gemm_activation(const ActivationLayerInfo &act)
Performs a mapping between Compute Library ActivationLayerInfo and the assembly Activation structure...
virtual unsigned int num_threads() const =0
Returns the number of threads that the SingleThreadScheduler has in his pool.
im2col_func configure(src_target.info(), dst_target.info(), spatial_kernel, conv_info, has_bias)
DataType
Available data types.
Definition: Types.h:77
signed 8-bit number
experimental::MemoryRequirements workspace() const override
Return the memory requirements required by the workspace.
static IScheduler & get()
Access the scheduler singleton.
Definition: Scheduler.cpp:94
unsigned int K