Compute Library
 21.11
CpuPool2dAssemblyWrapperKernel.cpp
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1 /*
2  * Copyright (c) 2021 Arm Limited.
3  *
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25 #include "arm_compute/core/Utils.h"
29 #include "src/core/CPP/Validate.h"
33 
34 #include <arm_neon.h>
35 
36 namespace arm_compute
37 {
38 namespace cpu
39 {
40 namespace kernels
41 {
43 
45 {
46  ARM_COMPUTE_UNUSED(cpu_info);
48 
49  // dst initialization if not yet initialized
50  auto_init_if_empty(*dst, src->clone()->set_tensor_shape(compute_pool_shape(*src, info)));
51 
52 #if defined(__aarch64__)
53  const bool requantize = src->quantization_info() != dst->quantization_info();
54 
55  switch(src->data_type())
56  {
57  case DataType::QASYMM8:
58  if(requantize)
59  {
60  create_arm_pooling_requant<uint8_t, uint8_t>(src, dst, info, cpu_info);
61  }
62  else
63  {
64  create_arm_pooling<uint8_t, uint8_t>(src, dst, info, cpu_info);
65  }
66  break;
68  if(requantize)
69  {
70  create_arm_pooling_requant<int8_t, int8_t>(src, dst, info, cpu_info);
71  }
72  else
73  {
74  create_arm_pooling<int8_t, int8_t>(src, dst, info, cpu_info);
75  }
76  break;
77 #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
78  case DataType::F16:
79  create_arm_pooling<float16_t, float16_t>(src, dst, info, cpu_info);
80  break;
81 #endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
82  case DataType::F32:
83  create_arm_pooling<float, float>(src, dst, info, cpu_info);
84  break;
85  default:
86  break;
87  }
88 #endif // defined(__aarch64__)
89 
90  Window win = calculate_max_window(*dst, Steps());
91  INEKernel::configure(win);
92 }
93 
95 {
97 
98 #ifndef __aarch64__
99  ARM_COMPUTE_RETURN_ERROR_MSG("32-bit is not supported by assembly kernels");
100 #endif /* __aarch64__ */
103  ARM_COMPUTE_RETURN_ERROR_ON_MSG((src->data_layout() != DataLayout::NHWC) || (info.data_layout != DataLayout::NHWC), "Only NHWC is supported by assembly kernels");
105  "Only AVG and MAX pooling are supported by assembly kernels");
106 
107  if(dst->total_size() > 0)
108  {
110 
111  const auto src_qinfo = src->quantization_info().uniform();
112  const auto dst_qinfo = dst->quantization_info().uniform();
113 
114  if(src_qinfo != dst_qinfo)
115  {
116  const float multiplier = src_qinfo.scale / dst_qinfo.scale;
117  int32_t dst_multiplier{};
118  int32_t dst_shift{};
119  ARM_COMPUTE_RETURN_ERROR_ON(quantization::calculate_quantized_multiplier(multiplier, &dst_multiplier, &dst_shift));
120  }
121  else
122  {
123  if(src->data_type() == DataType::QASYMM8)
124  {
125  const bool has_padding = info.pad_stride_info.has_padding();
126  ARM_COMPUTE_RETURN_ERROR_ON_MSG(!info.exclude_padding && has_padding, "Assembly kernels do not support padding for QASYMM8 with same src/dst quantization info");
127  }
128  }
129  }
130  else
131  {
132  if(src->data_type() == DataType::QASYMM8)
133  {
134  // If dst is not configured, the quantization info are the same
135  const bool has_padding = info.pad_stride_info.has_padding();
136  ARM_COMPUTE_RETURN_ERROR_ON_MSG(!info.exclude_padding && has_padding, "Assembly kernels do not support padding for QASYMM8 with same src/dst quantization info");
137  }
138  }
139  return Status{};
140 }
141 
143 {
144  ARM_COMPUTE_ERROR_ON_NULLPTR(_kernel_asm.get());
146  ARM_COMPUTE_UNUSED(window);
147  ARM_COMPUTE_UNUSED(info);
148 
149  ARM_COMPUTE_ERROR_ON(tensors.empty());
150 
153  ITensor *workspace = tensors.get_tensor(TensorType::ACL_INT_0);
154 
155  const auto in_ptr = src->buffer() + src->info()->offset_first_element_in_bytes();
156  auto out_ptr = dst->buffer() + dst->info()->offset_first_element_in_bytes();
157  auto working_space = workspace->buffer() + workspace->info()->offset_first_element_in_bytes();
158 
159  const auto src_shape = src->info()->tensor_shape();
160  const auto dst_shape = dst->info()->tensor_shape();
161  const auto src_padding = src->info()->padding();
162  const auto dst_padding = dst->info()->padding();
163 
164  const size_t ld_src_col = src_shape[0] + src_padding.left + src_padding.right;
165  const size_t ld_src_row = ld_src_col * (src_shape[1] + src_padding.top + src_padding.bottom);
166  const size_t ld_src_batch = ld_src_row * src_shape[2];
167  const size_t ld_dst_col = dst_shape[0] + dst_padding.left + dst_padding.right;
168  const size_t ld_dst_row = ld_dst_col * (dst_shape[1] + dst_padding.top + dst_padding.bottom);
169  const size_t ld_dst_batch = ld_dst_row * dst_shape[2];
170 
171  _kernel_asm->execute(in_ptr, ld_src_col, ld_src_row, ld_src_batch,
172  out_ptr, ld_dst_col, ld_dst_row, ld_dst_batch,
173  working_space, info.thread_id, info.num_threads);
174 }
175 
176 size_t CpuPool2dAssemblyWrapperKernel::get_working_size(unsigned int num_threads) const
177 {
178  return _kernel_asm->get_working_size(num_threads);
179 }
180 
182 {
183  return _kernel_asm != nullptr;
184 }
185 
186 template <typename Typesrc, typename Typedst>
187 void CpuPool2dAssemblyWrapperKernel::create_arm_pooling(const ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &info, const CPUInfo &cpu_info)
188 {
189  const arm_conv::pooling::PoolingType pool_type = (info.pool_type == PoolingType::AVG) ? arm_conv::pooling::PoolingType::AVERAGE : arm_conv::pooling::PoolingType::MAX;
190 
191  arm_conv::pooling::PoolingWindow window{};
192  window.cols = static_cast<unsigned int>(info.pool_size.x());
193  window.rows = static_cast<unsigned int>(info.pool_size.y());
194 
195  arm_conv::pooling::PoolingStride stride{};
196  std::tie(stride.cols, stride.rows) = info.pad_stride_info.stride();
197 
198  const arm_conv::PaddingValues padding{ info.pad_stride_info.pad_left(), info.pad_stride_info.pad_top(), info.pad_stride_info.pad_right(), info.pad_stride_info.pad_bottom() };
199 
200  constexpr unsigned int idx_width = 1;
201  constexpr unsigned int idx_height = 2;
202  constexpr unsigned int idx_channels = 0;
203  constexpr unsigned int idx_batches = 3;
204 
205  const unsigned int n_batches = src->dimension(idx_batches);
206  const unsigned int src_rows = src->dimension(idx_height);
207  const unsigned int src_cols = src->dimension(idx_width);
208  const unsigned int n_channels = src->dimension(idx_channels);
209  const unsigned int dst_rows = dst->dimension(idx_height);
210  const unsigned int dst_cols = dst->dimension(idx_width);
211 
212  arm_conv::pooling::PoolingArgs args(&cpu_info, pool_type, window, stride, info.exclude_padding, n_batches, src_rows, src_cols, n_channels, dst_rows, dst_cols, padding, nullptr);
213 
214  // Configure assembly pooling kernel
215  auto pooling_kernel_asm = arm_conv::pooling::pooling<Typesrc, Typedst>(args);
216  if(pooling_kernel_asm == nullptr)
217  {
218  // Configuration not supported: Leave function unconfigured:
219  return;
220  }
221 
222  _kernel_asm = std::move(pooling_kernel_asm);
223 }
224 
225 template <typename Typesrc, typename Typedst>
226 void CpuPool2dAssemblyWrapperKernel::create_arm_pooling_requant(const ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &info, const CPUInfo &cpu_info)
227 {
228  const arm_conv::pooling::PoolingType pool_type = (info.pool_type == PoolingType::AVG) ? arm_conv::pooling::PoolingType::AVERAGE : arm_conv::pooling::PoolingType::MAX;
229 
230  arm_conv::pooling::PoolingWindow window{};
231  window.cols = static_cast<unsigned int>(info.pool_size.x());
232  window.rows = static_cast<unsigned int>(info.pool_size.y());
233 
234  arm_conv::pooling::PoolingStride stride{};
235  std::tie(stride.cols, stride.rows) = info.pad_stride_info.stride();
236 
237  const arm_conv::PaddingValues padding{ info.pad_stride_info.pad_left(), info.pad_stride_info.pad_top(), info.pad_stride_info.pad_right(), info.pad_stride_info.pad_bottom() };
238 
239  constexpr unsigned int idx_width = 1;
240  constexpr unsigned int idx_height = 2;
241  constexpr unsigned int idx_channels = 0;
242  constexpr unsigned int idx_batches = 3;
243 
244  const unsigned int n_batches = src->dimension(idx_batches);
245  const unsigned int src_rows = src->dimension(idx_height);
246  const unsigned int src_cols = src->dimension(idx_width);
247  const unsigned int n_channels = src->dimension(idx_channels);
248  const unsigned int dst_rows = dst->dimension(idx_height);
249  const unsigned int dst_cols = dst->dimension(idx_width);
250 
251  arm_conv::pooling::PoolingArgs args(&cpu_info, pool_type, window, stride, info.exclude_padding, n_batches, src_rows, src_cols, n_channels, dst_rows, dst_cols, padding, nullptr);
252 
253  const auto src_qinfo = src->quantization_info().uniform();
254  const auto dst_qinfo = dst->quantization_info().uniform();
255 
256  const float multiplier = src_qinfo.scale / dst_qinfo.scale;
257  int32_t dst_multiplier{};
258  int32_t dst_shift{};
259  quantization::calculate_quantized_multiplier(multiplier, &dst_multiplier, &dst_shift);
260 
261  const arm_conv::pooling::Requantize32 requant_args(src_qinfo.offset,
262  dst_qinfo.offset,
263  dst_shift, // left shift
264  0, // right shift
265  dst_multiplier);
266 
267  // Configure assembly pooling kernel with requantization
268  auto pooling_kernel_asm = arm_conv::pooling::pooling<Typesrc, Typedst, arm_conv::pooling::Requantize32>(args, requant_args);
269  if(pooling_kernel_asm == nullptr)
270  {
271  // Configuration not supported: Leave function unconfigured:
272  return;
273  }
274 
275  _kernel_asm = std::move(pooling_kernel_asm);
276 }
277 
278 size_t CpuPool2dAssemblyWrapperKernel::get_mws(const CPUInfo &platform, size_t thread_count) const
279 {
280  ARM_COMPUTE_UNUSED(platform, thread_count);
281 
283 }
284 } // namespace kernels
285 } // namespace cpu
286 } // namespace arm_compute
Window calculate_max_window(const ValidRegion &valid_region, const Steps &steps, bool skip_border, BorderSize border_size)
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:115
virtual size_t dimension(size_t index) const =0
Return the size of the requested dimension.
static constexpr size_t small_network_mws
Definition: ICPPKernel.h:42
bool empty() const
Checks if pack is empty.
Definition: ITensorPack.cpp:80
virtual DataType data_type() const =0
Data type used for each element of the tensor.
1 channel, 1 F32 per channel
#define MAX(x, y)
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
size_t x() const
Semantic accessor for width as x.
Definition: Size2D.h:75
unsigned int pad_top() const
Get the top padding.
Definition: Types.h:740
Status calculate_quantized_multiplier(float multiplier, int32_t *quant_multiplier, int32_t *shift, bool ignore_epsilon=false)
Calculate quantized representation of multiplier.
Status class.
Definition: Error.h:52
#define ARM_COMPUTE_RETURN_ERROR_ON(cond)
If the condition is true, an error is returned.
Definition: Error.h:296
Interface for CPU tensor.
Definition: ITensor.h:36
SimpleTensor< float > src
Definition: DFT.cpp:155
Copyright (c) 2017-2021 Arm Limited.
1 channel, 1 F16 per channel
#define ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(...)
Definition: Validate.h:159
TensorShape compute_pool_shape(const ITensorInfo &input, PoolingLayerInfo pool_info)
Calculate the output pool shape of a tensor.
const ITensor * get_const_tensor(int id) const
Get constant tensor of a given id.
Definition: ITensorPack.cpp:54
void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override
Execute the kernel on the passed window.
bool is_configured() const
Was the asm kernel successfully configured?
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
virtual const TensorShape & tensor_shape() const =0
Size for each dimension of the tensor.
quantized, asymmetric fixed-point 8-bit number unsigned
Class to describe a number of elements in each dimension.
Definition: Steps.h:40
virtual uint8_t * buffer() const =0
Interface to be implemented by the child class to return a pointer to CPU memory. ...
std::pair< unsigned int, unsigned int > stride() const
Get the stride.
Definition: Types.h:704
Pooling Layer Information struct.
Definition: Types.h:1173
UniformQuantizationInfo uniform() const
Return per layer quantization info.
bool auto_init_if_empty(ITensorInfo &info, const TensorShape &shape, int num_channels, DataType data_type, QuantizationInfo quantization_info=QuantizationInfo())
Auto initialize the tensor info (shape, number of channels and data type) if the current assignment i...
virtual std::unique_ptr< T > clone() const =0
Provide a clone of the current object of class T.
virtual ITensorInfo * info() const =0
Interface to be implemented by the child class to return the tensor&#39;s metadata.
unsigned int pad_right() const
Get the right padding.
Definition: Types.h:735
virtual PaddingSize padding() const =0
Padding of tensor.
unsigned int left
left of the border
Definition: Types.h:380
virtual QuantizationInfo quantization_info() const =0
Get the quantization settings (scale and offset) of the tensor.
#define ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(k)
Definition: Validate.h:915
size_t y() const
Semantic accessor for height as y.
Definition: Size2D.h:84
virtual size_t offset_first_element_in_bytes() const =0
The offset from the beginning of the memory allocation to the first element of the tensor...
PoolingType
Available pooling types.
Definition: Types.h:544
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
ITensor * get_tensor(int id)
Get tensor of a given id from the pac.
Definition: ITensorPack.cpp:64
size_t get_working_size(unsigned int num_threads) const
Get size of the workspace needed by the assembly kernel.
#define ARM_COMPUTE_RETURN_ERROR_MSG(...)
An error is returned with the given description.
Definition: Error.h:194
PadStrideInfo pad_stride_info
Definition: Types.h:1261
Information about executing thread and CPU.
Definition: CPPTypes.h:158
virtual size_t total_size() const =0
Returns the total size of the tensor in bytes.
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:541
Num samples, height, width, channels.
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:788
#define ARM_COMPUTE_RETURN_ERROR_ON_MSG(cond, msg)
If the condition is true, an error is returned.
Definition: Error.h:244
Tensor packing service.
Definition: ITensorPack.h:39
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:157
quantized, asymmetric fixed-point 8-bit number signed
static Status validate(const ITensorInfo *src, const ITensorInfo *dst, const PoolingLayerInfo &info)
Static function to check if given info will lead to a valid configuration.
unsigned int pad_bottom() const
Get the bottom padding.
Definition: Types.h:745
void configure(const ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &info, const CPUInfo &cpu_info)
Initialise the kernel&#39;s src and dst.
unsigned int pad_left() const
Get the left padding.
Definition: Types.h:730
Describe a multidimensional execution window.
Definition: Window.h:39
virtual DataLayout data_layout() const =0
Get the data layout of the tensor.
bool has_padding() const
Check whether this has any padding.
Definition: Types.h:757