Compute Library
 21.02
NEDepthwiseConvolutionAssemblyDispatch.cpp
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24 
26 
28 #include "arm_compute/core/Utils.h"
32 #include "src/core/CPP/Validate.h"
33 #include "src/core/NEON/kernels/assembly/NEDepthwiseConvolutionAssemblyKernelWrapper.h"
34 #include "src/core/NEON/kernels/convolution/depthwise/depthwise_dilated.hpp"
35 #include "src/core/NEON/kernels/convolution/depthwise/depthwise_quantized_dilated.hpp"
37 
39 
40 #include <set>
41 
42 namespace arm_compute
43 {
44 namespace
45 {
46 std::unique_ptr<depthwise::IDepthwiseConvolution> get_qasymm8_convolver(int kernel_size, int stride_x,
47  int n_batches, int in_rows, int in_cols, int n_channels,
48  int dilation_factor, neon_convolution_kernels::ActivationFunction activation,
49  const qasymm8::QAsymm8Params &wqinfo, const qasymm8::QAsymm8Params &iqinfo, const qasymm8::QAsymm8Params &oqinfo,
50  const qasymm8::QAsymm8RescaleParams &rescale_params,
51  int padding_top, int padding_left, int padding_bottom, int padding_right)
52 {
53  switch(kernel_size)
54  {
55  case 3:
56  {
57  switch(stride_x)
58  {
59  case 1:
60  return std::make_unique<depthwise::QAsymm8DilatedDepthwiseConvolution<2, 2, 3, 3, 1, 1>>(
61  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
62  case 2:
63  return std::make_unique<depthwise::QAsymm8DilatedDepthwiseConvolution<2, 2, 3, 3, 2, 2>>(
64  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
65  default:
66  return nullptr;
67  }
68  }
69  case 5:
70  {
71  switch(stride_x)
72  {
73  case 1:
74  return std::make_unique<depthwise::QAsymm8DilatedDepthwiseConvolution<2, 2, 5, 5, 1, 1>>(
75  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
76  case 2:
77  return std::make_unique<depthwise::QAsymm8DilatedDepthwiseConvolution<2, 2, 5, 5, 2, 2>>(
78  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
79  default:
80  return nullptr;
81  }
82  }
83  default:
84  return nullptr;
85  }
86 }
87 
88 std::unique_ptr<depthwise::IDepthwiseConvolution> get_qsymm8_perchannel_convolver(int kernel_size, int stride_x,
89  int n_batches, int in_rows, int in_cols, int n_channels,
90  neon_convolution_kernels::ActivationFunction activation,
91  const qsymm8::QSymm8PerChannelParams &wqinfo, const qasymm8::QAsymm8Params &iqinfo, const qasymm8::QAsymm8Params &oqinfo,
92  const qsymm8::QSymm8PerChannelRescaleParams &rescale_params,
93  int padding_top, int padding_left, int padding_bottom, int padding_right)
94 {
95  switch(kernel_size)
96  {
97  case 3:
98  {
99  switch(stride_x)
100  {
101  case 1:
102  return std::make_unique<depthwise::QSymm8HybridPerChannelDepthwiseConvolution<2, 2, 3, 3, 1, 1>>(
103  n_batches, in_rows, in_cols, n_channels, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
104  case 2:
105  return std::make_unique<depthwise::QSymm8HybridPerChannelDepthwiseConvolution<2, 2, 3, 3, 2, 2>>(
106  n_batches, in_rows, in_cols, n_channels, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
107  default:
108  return nullptr;
109  }
110  }
111  case 5:
112  {
113  switch(stride_x)
114  {
115  case 1:
116  return std::make_unique<depthwise::QSymm8HybridPerChannelDepthwiseConvolution<2, 2, 5, 5, 1, 1>>(
117  n_batches, in_rows, in_cols, n_channels, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
118  case 2:
119  return std::make_unique<depthwise::QSymm8HybridPerChannelDepthwiseConvolution<2, 2, 5, 5, 2, 2>>(
120  n_batches, in_rows, in_cols, n_channels, activation, wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
121  default:
122  return nullptr;
123  }
124  }
125  default:
126  return nullptr;
127  }
128 }
129 
130 #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
131 std::unique_ptr<depthwise::IDepthwiseConvolution> get_fp16_convolver(int kernel_size, int stride_x,
132  int n_batches, int in_rows, int in_cols, int n_channels,
133  int dilation_factor, neon_convolution_kernels::ActivationFunction activation,
134  int padding_top, int padding_left, int padding_bottom, int padding_right)
135 {
136  switch(kernel_size)
137  {
138  case 3:
139  {
140  switch(stride_x)
141  {
142  case 1:
143  return std::make_unique<depthwise::DilatedDepthwiseConvolution<3, 3, 3, 3, 1, 1, float16_t, float16_t, float16_t>>(
144  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
145  case 2:
146  return std::make_unique<depthwise::DilatedDepthwiseConvolution<3, 3, 3, 3, 2, 2, float16_t, float16_t, float16_t>>(
147  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
148  default:
149  return nullptr;
150  }
151  }
152  case 5:
153  {
154  switch(stride_x)
155  {
156  case 1:
157  return std::make_unique<depthwise::DilatedDepthwiseConvolution<3, 3, 5, 5, 1, 1, float16_t, float16_t, float16_t>>(
158  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
159  case 2:
160  return std::make_unique<depthwise::DilatedDepthwiseConvolution<3, 3, 5, 5, 2, 2, float16_t, float16_t, float16_t>>(
161  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
162  default:
163  return nullptr;
164  }
165  }
166  default:
167  return nullptr;
168  }
169 }
170 #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
171 
172 std::unique_ptr<depthwise::IDepthwiseConvolution> get_fp32_convolver(int kernel_size, int stride_x,
173  int n_batches, int in_rows, int in_cols, int n_channels,
174  int dilation_factor, neon_convolution_kernels::ActivationFunction activation,
175  int padding_top, int padding_left, int padding_bottom, int padding_right)
176 {
177  switch(kernel_size)
178  {
179  case 3:
180  {
181  switch(stride_x)
182  {
183  case 1:
184  return std::make_unique<depthwise::DilatedDepthwiseConvolution<4, 4, 3, 3, 1, 1, float, float, float>>(
185  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
186  case 2:
187  return std::make_unique<depthwise::DilatedDepthwiseConvolution<3, 3, 3, 3, 2, 2, float, float, float>>(
188  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
189  default:
190  return nullptr;
191  }
192  }
193  case 5:
194  {
195  switch(stride_x)
196  {
197  case 1:
198  return std::make_unique<depthwise::DilatedDepthwiseConvolution<4, 4, 5, 5, 1, 1, float, float, float>>(
199  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
200  case 2:
201  return std::make_unique<depthwise::DilatedDepthwiseConvolution<3, 3, 5, 5, 2, 2, float, float, float>>(
202  n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
203  default:
204  return nullptr;
205  }
206  }
207  default:
208  return nullptr;
209  }
210 }
211 
212 std::unique_ptr<depthwise::IDepthwiseConvolution> create_convolver(const ITensor *input,
213  const ITensor *weights,
214  ITensor *output,
215  PadStrideInfo conv_info,
216  ActivationLayerInfo act_info,
217  const Size2D &dilation)
218 {
219  ARM_COMPUTE_UNUSED(dilation);
220  const DataType data_type = input->info()->data_type();
221  const TensorShape shape = input->info()->tensor_shape();
222 
223  const int n_batches = shape[3];
224  const int in_rows = shape.z();
225  const int in_cols = shape.y();
226  const int n_channels = shape.x();
227  const int dilation_factor = dilation.x();
228  const int padding_top = conv_info.pad_top();
229  const int padding_left = conv_info.pad_left();
230  const int padding_bottom = conv_info.pad_bottom();
231  const int padding_right = conv_info.pad_right();
232 
233  const bool is_uniform_quantized = (data_type == DataType::QASYMM8) && (weights->info()->data_type() == DataType::QASYMM8);
234  const bool is_perchannel_quantized = (data_type == DataType::QASYMM8) && (weights->info()->data_type() == DataType::QSYMM8_PER_CHANNEL);
235 
236  const unsigned int stride_x = conv_info.stride().first;
237  const unsigned int kernel_size = weights->info()->tensor_shape().y();
238 
239  // Map activation function
240  neon_convolution_kernels::ActivationFunction activation = neon_convolution_kernels::ActivationFunction::None;
242  {
243  activation = neon_convolution_kernels::ActivationFunction::ReLU;
244  }
246  {
247  activation = neon_convolution_kernels::ActivationFunction::ReLU6;
248  }
249 
250  // Create quantized convolver
251  if(is_uniform_quantized)
252  {
253  const UniformQuantizationInfo input_qinfo = input->info()->quantization_info().uniform();
254  const UniformQuantizationInfo weights_qinfo = weights->info()->quantization_info().uniform();
255  const UniformQuantizationInfo output_qinfo = output->info()->quantization_info().uniform();
256 
257  // Check that quantization info are in the range [0, 255]
258  ARM_COMPUTE_ERROR_ON(input_qinfo.offset < 0 || input_qinfo.offset > 255);
259  ARM_COMPUTE_ERROR_ON(weights_qinfo.offset < 0 || weights_qinfo.offset > 255);
260  ARM_COMPUTE_ERROR_ON(output_qinfo.offset < 0 || output_qinfo.offset > 255);
261  const qasymm8::QAsymm8Params iqinfo{ static_cast<uint8_t>(input_qinfo.offset), input_qinfo.scale };
262  const qasymm8::QAsymm8Params wqinfo{ static_cast<uint8_t>(weights_qinfo.offset), weights_qinfo.scale };
263  const qasymm8::QAsymm8Params oqinfo{ static_cast<uint8_t>(output_qinfo.offset), output_qinfo.scale };
264 
265  // Calculate rescale parameters
266  const float fmultipler = iqinfo.scale * wqinfo.scale / oqinfo.scale;
267  int32_t qmultiplier = 0;
268  int32_t qshift = 0;
269  quantization::calculate_quantized_multiplier_less_than_one(fmultipler, &qmultiplier, &qshift);
270  qasymm8::QAsymm8RescaleParams rescale_params(qshift, qmultiplier, fmultipler);
271 
272  return get_qasymm8_convolver(kernel_size, stride_x, n_batches, in_rows, in_cols, n_channels, dilation_factor, activation,
273  wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
274  }
275  else if(is_perchannel_quantized)
276  {
277  const UniformQuantizationInfo input_qinfo = input->info()->quantization_info().uniform();
278  const QuantizationInfo weights_qinfo = weights->info()->quantization_info();
279  const UniformQuantizationInfo output_qinfo = output->info()->quantization_info().uniform();
280 
281  // Check that quantization info are in the range [0, 255]
282  ARM_COMPUTE_ERROR_ON(input_qinfo.offset < 0 || input_qinfo.offset > 255);
283  ARM_COMPUTE_ERROR_ON(output_qinfo.offset < 0 || output_qinfo.offset > 255);
284  const qasymm8::QAsymm8Params iqinfo{ static_cast<uint8_t>(input_qinfo.offset), input_qinfo.scale };
285  const qsymm8::QSymm8PerChannelParams wqinfo{ weights_qinfo.scale() };
286  const qasymm8::QAsymm8Params oqinfo{ static_cast<uint8_t>(output_qinfo.offset), output_qinfo.scale };
287 
288  // Calculate rescale parameters
289  std::vector<float> fmultipliers;
290  std::vector<int32_t> qmultipliers;
291  std::vector<int32_t> qshifts;
292 
293  for(auto const s : wqinfo.scales)
294  {
295  const float fmultipler = iqinfo.scale * s / oqinfo.scale;
296  int32_t qmultiplier = 0;
297  int32_t qshift = 0;
298  quantization::calculate_quantized_multiplier_less_than_one(fmultipler, &qmultiplier, &qshift);
299  fmultipliers.push_back(fmultipler);
300  qmultipliers.push_back(qmultiplier);
301  qshifts.push_back(qshift);
302  }
303 
304  qsymm8::QSymm8PerChannelRescaleParams rescale_params(qshifts, qmultipliers, fmultipliers);
305 
306  return get_qsymm8_perchannel_convolver(kernel_size, stride_x, n_batches, in_rows, in_cols, n_channels, activation,
307  wqinfo, iqinfo, oqinfo, rescale_params, padding_top, padding_left, padding_bottom, padding_right);
308  }
309  else
310  {
311  // Create float convolver
312  switch(data_type)
313  {
314 #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
315  case DataType::F16:
316  {
317  return get_fp16_convolver(kernel_size, stride_x, n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
318  }
319 #endif // __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
320  case DataType::F32:
321  {
322  return get_fp32_convolver(kernel_size, stride_x, n_batches, in_rows, in_cols, n_channels, dilation_factor, activation, padding_top, padding_left, padding_bottom, padding_right);
323  }
324  default:
325  return nullptr;
326  }
327  }
328 }
329 } // namespace
330 
331 struct NEDepthwiseConvolutionAssemblyDispatch::LocalImpl
332 {
333  std::unique_ptr<depthwise::IDepthwiseConvolution> _dwc_assembly_kernel{ nullptr };
334  NEDepthwiseConvolutionAssemblyKernelWrapper _dwc_acl_kernel{};
335 };
336 
337 #ifndef DOXYGEN_SKIP_THIS
338 NEDepthwiseConvolutionAssemblyDispatch::NEDepthwiseConvolutionAssemblyDispatch(std::shared_ptr<arm_compute::IMemoryManager> memory_manager)
339  : _memory_group(std::move(memory_manager)), _input(nullptr), _weights(nullptr), _bias(nullptr), _output(nullptr), _packed_weights(), _workspace(), _is_prepared(false),
340  _pImpl(std::make_unique<LocalImpl>())
341 {
342 }
343 #endif /* DOXYGEN_SKIP_THIS */
344 
346 
348  const ITensor *weights,
349  const ITensor *bias,
350  ITensor *output,
351  const PadStrideInfo &conv_info,
352  unsigned int depth_multiplier,
353  const ActivationLayerInfo &act_info,
354  const Size2D &dilation)
355 {
356  ARM_COMPUTE_ERROR_ON_NULLPTR(input, weights, output);
357  ARM_COMPUTE_UNUSED(depth_multiplier);
359  weights->info(),
360  bias != nullptr ? bias->info() : nullptr,
361  output->info(),
362  conv_info,
363  depth_multiplier,
364  act_info,
365  dilation));
366 
367  // Output auto inizialitation if not yet initialized
368  const TensorShape output_shape = misc::shape_calculator::compute_depthwise_convolution_shape(*input->info(), *weights->info(), conv_info, depth_multiplier, dilation);
369  auto_init_if_empty(*output->info(), input->info()->clone()->set_is_resizable(true).reset_padding().set_tensor_shape(output_shape).set_quantization_info(output->info()->quantization_info()));
370 
371  _input = input;
372  _weights = weights;
373  _bias = bias;
374  _output = output;
375  _is_prepared = false;
376 
377  // Create convolver
378  _pImpl->_dwc_assembly_kernel = create_convolver(input, weights, output, conv_info, act_info, dilation);
379  ARM_COMPUTE_ERROR_ON(_pImpl->_dwc_assembly_kernel == nullptr);
380 
381  // Create assembly kernel wrapper
382  _pImpl->_dwc_acl_kernel.configure(_pImpl->_dwc_assembly_kernel.get());
383 
384  constexpr size_t alignment = 128;
385 
386  // Create workspace
387  const unsigned int num_threads = NEScheduler::get().num_threads();
388  const size_t workspace_size = _pImpl->_dwc_assembly_kernel->get_working_space_size(num_threads);
389  ARM_COMPUTE_ERROR_ON_MSG(workspace_size == 0, "Workspace size cannot be 0 !");
390  _workspace.allocator()->init(TensorInfo(TensorShape{ workspace_size }, 1, DataType::S8), alignment);
391  _memory_group.manage(&_workspace);
392  _workspace.allocator()->allocate();
393 
394  // Create packing tensor
395  const size_t pack_tensor_size = _pImpl->_dwc_assembly_kernel->get_packed_params_size();
396  ARM_COMPUTE_ERROR_ON_MSG(pack_tensor_size == 0, "Pack tensor size cannot be 0 !");
397  _packed_weights.allocator()->init(TensorInfo(TensorShape{ pack_tensor_size }, 1, DataType::S8), alignment);
398 }
399 
401  const ITensorInfo *weights,
402  const ITensorInfo *bias,
403  const ITensorInfo *output,
404  const PadStrideInfo &conv_info,
405  unsigned int depth_multiplier,
406  const ActivationLayerInfo &act_info,
407  const Size2D &dilation)
408 {
411  if(weights->data_type() != DataType::QSYMM8_PER_CHANNEL)
412  {
414  }
416 
417  // Validate convolver
418  ARM_COMPUTE_RETURN_ERROR_ON(!is_optimized_supported(input, weights, conv_info, depth_multiplier, dilation));
419 
420  // Validate activation
421  const bool is_relu = arm_compute::utils::info_helpers::is_relu(act_info);
423  ARM_COMPUTE_RETURN_ERROR_ON(act_info.enabled() && !(is_relu || is_relu6));
424 
425  // Check bias
426  if(bias != nullptr)
427  {
428  unsigned int channel_idx = get_data_layout_dimension_index(input->data_layout(), DataLayoutDimension::CHANNEL);
430  ARM_COMPUTE_RETURN_ERROR_ON(bias->dimension(0) != weights->dimension(channel_idx));
431  }
432 
433  // Check output
434  if(output->total_size() != 0)
435  {
436  const TensorShape output_shape = misc::shape_calculator::compute_depthwise_convolution_shape(*input, *weights, conv_info, depth_multiplier, dilation);
439  }
440 
441  // The uniform quantization case will only have 1 scale value in the weights quantization info
442  const UniformQuantizationInfo input_qinfo = input->quantization_info().uniform();
443  const QuantizationInfo weights_qinfo = weights->quantization_info();
444  const UniformQuantizationInfo output_qinfo = output->quantization_info().uniform();
445  for(auto const s : weights_qinfo.scale())
446  {
447  const float fmultipler = input_qinfo.scale * s / output_qinfo.scale;
448  ARM_COMPUTE_RETURN_ERROR_ON(fmultipler > 1.f);
449  }
450 
451  return Status{};
452 }
453 
455  const ITensorInfo *weights,
456  PadStrideInfo conv_info,
457  unsigned int depth_multiplier,
458  const Size2D &dilation)
459 {
460  ARM_COMPUTE_ERROR_ON_NULLPTR(input, weights);
461 
462  // Reshape input shape if in NHWC format
463  const DataLayout data_layout = input->data_layout();
464  TensorShape in_shape{ input->tensor_shape() };
465  if(data_layout == DataLayout::NHWC)
466  {
467  in_shape.set(Window::DimX, input->tensor_shape().y());
468  in_shape.set(Window::DimY, input->tensor_shape().z());
469  in_shape.set(Window::DimZ, input->tensor_shape().x());
470  }
471 
472  // Check data type
473  // TODO (COMPMID-3004): Add assembly optimized routine for QASYMM8_SIGNED NEDepthwiseConvolutionLayer
474  const DataType input_type = input->data_type();
475  const bool is_input_type_valid = is_data_type_float(input_type) || input_type == DataType::QASYMM8;
476  const DataType weights_type = weights->data_type();
477  const bool is_weights_type_valid = is_data_type_float(weights_type) || weights_type == DataType::QASYMM8 || weights_type == DataType::QASYMM8_SIGNED
478  || weights_type == DataType::QSYMM8_PER_CHANNEL;
479 
480  // Check weighs size
481  std::set<unsigned int> supported_kernel_sizes = { 3, 5 };
482  const unsigned int width_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::WIDTH);
483  const unsigned int height_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::HEIGHT);
484  const unsigned int kernel_w = weights->dimension(width_idx);
485  const unsigned int kernel_h = weights->dimension(height_idx);
486  bool weights_supported = (kernel_w == kernel_h) && (supported_kernel_sizes.count(kernel_w) != 0);
487 
488  // Check for supported strides
489  const auto &strides = conv_info.stride();
490  bool supported_strides = (strides.first == strides.second) && ((strides.first == 1) || (strides.first == 2));
491 
492  // Check for supported padding
493  const auto pad_top = conv_info.pad_top();
494  const auto pad_right = conv_info.pad_right();
495  const auto pad_bottom = conv_info.pad_bottom();
496  const auto pad_left = conv_info.pad_left();
497  PadStrideInfo same_pad = calculate_same_pad(in_shape, TensorShape(kernel_w, kernel_h), conv_info, DataLayout::NCHW, dilation);
498  bool is_same_padding = (pad_top == same_pad.pad_top()) && (pad_right == same_pad.pad_right()) && (pad_bottom == same_pad.pad_bottom()) && (pad_left == same_pad.pad_left());
499  bool is_valid_padding = (pad_top == 0) && (pad_right == 0) && (pad_bottom == 0) && (pad_left == 0);
500  bool supported_padding = is_same_padding || is_valid_padding;
501  // TODO(COMPMID-2464): Enable once dilated conv with stride 2 is supported
502  bool is_dilation_supported = ((dilation == Size2D(1U, 1U)) || ((dilation.x() == dilation.y()) && strides.first == 1));
503 
504  if(weights_type == DataType::QSYMM8_PER_CHANNEL)
505  {
506  is_dilation_supported = is_dilation_supported && (dilation == Size2D(1U, 1U));
507  }
508 
509  return is_input_type_valid && is_weights_type_valid && weights_supported && supported_strides && supported_padding && (depth_multiplier == 1) && is_dilation_supported;
510 }
511 
513 {
514  // Prepare assembly kernel
515  prepare();
516 
517  MemoryGroupResourceScope scope_mg(_memory_group);
518 
519  // Setup inputs/outputs
520  ARM_COMPUTE_ERROR_ON(_workspace.buffer() == nullptr);
521  _pImpl->_dwc_assembly_kernel->set_working_space(static_cast<void *>(_workspace.buffer()));
522 
523  ARM_COMPUTE_ERROR_ON(_input->buffer() == nullptr);
524  const int input_element_size = _input->info()->element_size();
525  const int input_batch_stride = _input->info()->strides_in_bytes()[3] / input_element_size;
526  const int input_row_stride = _input->info()->strides_in_bytes().z() / input_element_size;
527  const int input_col_stride = _input->info()->strides_in_bytes().y() / input_element_size;
528  const void *input_ptr = _input->buffer() + _input->info()->offset_first_element_in_bytes();
529  _pImpl->_dwc_assembly_kernel->set_input(input_ptr, input_batch_stride, input_row_stride, input_col_stride);
530 
531  ARM_COMPUTE_ERROR_ON(_output->buffer() == nullptr);
532  const int output_element_size = _output->info()->element_size();
533  const int output_batch_stride = _output->info()->strides_in_bytes()[3] / output_element_size;
534  const int output_row_stride = _output->info()->strides_in_bytes().z() / output_element_size;
535  const int output_col_stride = _output->info()->strides_in_bytes().y() / output_element_size;
536  void *output_ptr = _output->buffer() + _output->info()->offset_first_element_in_bytes();
537  _pImpl->_dwc_assembly_kernel->set_output(output_ptr, output_batch_stride, output_row_stride, output_col_stride);
538 
539  // Schedule assembly kernel
540  NEScheduler::get().schedule(&_pImpl->_dwc_acl_kernel, Window::DimX);
541 }
542 
544 {
545  if(!_is_prepared)
546  {
547  _packed_weights.allocator()->allocate();
548  ARM_COMPUTE_ERROR_ON(_packed_weights.buffer() == nullptr);
549 
550  // Pack weights and bias
551  const int weights_element_size = _weights->info()->element_size();
552  const int weights_row_stride = _weights->info()->strides_in_bytes().z() / weights_element_size;
553  const int weights_col_stride = _weights->info()->strides_in_bytes().y() / weights_element_size;
554  _pImpl->_dwc_assembly_kernel->pack_params(_packed_weights.buffer(),
555  _weights->buffer() + _weights->info()->offset_first_element_in_bytes(),
556  weights_row_stride,
557  weights_col_stride,
558  (_bias != nullptr) ? _bias->buffer() : nullptr);
559  _pImpl->_dwc_assembly_kernel->set_packed_params_buffer(_packed_weights.buffer());
560 
561  _weights->mark_as_unused();
562  if(_bias != nullptr)
563  {
564  _bias->mark_as_unused();
565  }
566  _is_prepared = true;
567  }
568 }
569 } // namespace arm_compute
virtual size_t num_dimensions() const =0
The number of dimensions of the tensor (rank)
Shape of a tensor.
Definition: TensorShape.h:39
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(...)
Definition: Validate.h:494
#define ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(tensor)
Definition: Validate.h:108
TensorShape compute_depthwise_convolution_shape(const ITensorInfo &input, const ITensorInfo &weights, PadStrideInfo conv_info, unsigned int depth_multiplier, const Size2D &dilation=Size2D(1U, 1U))
Calculate the depthwise convolution output shape of a tensor.
bool enabled() const
Check if initialised.
Definition: Types.h:1600
virtual size_t dimension(size_t index) const =0
Return the size of the requested dimension.
virtual DataType data_type() const =0
Data type used for each element of the tensor.
static Status validate(const ITensorInfo *input, const ITensorInfo *weights, const ITensorInfo *bias, const ITensorInfo *output, const PadStrideInfo &conv_info, unsigned int depth_multiplier=1, const ActivationLayerInfo &act_info=ActivationLayerInfo(), const Size2D &dilation=Size2D(1, 1))
Static function to check if given info will lead to a valid configuration of NEDepthwiseConvolutionAs...
1 channel, 1 F32 per channel
#define ARM_COMPUTE_ERROR_ON(cond)
If the condition is true then an error message is printed and an exception thrown.
Definition: Error.h:466
void prepare() override
Prepare the function for executing.
const DataLayout data_layout
Definition: Im2Col.cpp:151
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
#define ARM_COMPUTE_ERROR_THROW_ON(status)
Definition: Error.h:455
Quantization info when assuming per layer quantization.
size_t x() const
Semantic accessor for width as x.
Definition: Size2D.h:74
unsigned int pad_top() const
Get the top padding.
Definition: Types.h:806
Status class.
Definition: Error.h:52
#define ARM_COMPUTE_RETURN_ERROR_ON(cond)
If the condition is true, an error is returned.
Definition: Error.h:296
Activation Layer Information class.
Definition: Types.h:1550
Interface for Neon tensor.
Definition: ITensor.h:36
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(...)
Definition: Validate.h:288
Copyright (c) 2017-2021 Arm Limited.
1 channel, 1 F16 per channel
NEDepthwiseConvolutionAssemblyDispatch(std::shared_ptr< IMemoryManager > memory_manager=nullptr)
Default constructor.
T x() const
Alias to access the size of the first dimension.
Definition: Dimensions.h:87
const DataType data_type
Definition: Im2Col.cpp:150
Quantization information.
static constexpr size_t DimX
Alias for dimension 0 also known as X dimension.
Definition: Window.h:43
#define ARM_COMPUTE_UNUSED(...)
To avoid unused variables warnings.
Definition: Error.h:152
virtual const TensorShape & tensor_shape() const =0
Size for each dimension of the tensor.
quantized, asymmetric fixed-point 8-bit number unsigned
T z() const
Alias to access the size of the third dimension.
Definition: Dimensions.h:97
#define ARM_COMPUTE_ERROR_ON_MSG(cond, msg)
Definition: Error.h:456
std::pair< unsigned int, unsigned int > stride() const
Get the stride.
Definition: Types.h:770
UniformQuantizationInfo uniform() const
Return per layer quantization info.
bool auto_init_if_empty(ITensorInfo &info, const TensorShape &shape, int num_channels, DataType data_type, QuantizationInfo quantization_info=QuantizationInfo())
Auto initialize the tensor info (shape, number of channels and data type) if the current assignment i...
virtual std::unique_ptr< T > clone() const =0
Provide a clone of the current object of class T.
virtual ITensorInfo * info() const =0
Interface to be implemented by the child class to return the tensor&#39;s metadata.
unsigned int pad_right() const
Get the right padding.
Definition: Types.h:801
const std::vector< float > & scale() const
Scale vector accessor.
void configure(const ITensor *input, const ITensor *weights, const ITensor *bias, ITensor *output, const PadStrideInfo &conv_info, unsigned int depth_multiplier=1, const ActivationLayerInfo &act_info=ActivationLayerInfo(), const Size2D &dilation=Size2D(1, 1))
Initialize the function&#39;s source, destination, kernels and border_size.
Padding and stride information class.
Definition: Types.h:722
static bool is_optimized_supported(const ITensorInfo *input, const ITensorInfo *weights, PadStrideInfo conv_info, unsigned int depth_multiplier=1, const Size2D &dilation=Size2D(1, 1))
Check if the optimized kernel can be used for the given kernel sizes and strides. ...
virtual QuantizationInfo quantization_info() const =0
Get the quantization settings (scale and offset) of the tensor.
Num samples, channels, height, width.
size_t y() const
Semantic accessor for height as y.
Definition: Size2D.h:83
bool is_relu6(ActivationLayerInfo activation_info)
Checks if activation information correspond to a relu6 activation function.
Definition: InfoHelpers.h:54
quantized, symmetric per channel fixed-point 8-bit number
static constexpr size_t DimY
Alias for dimension 1 also known as Y dimension.
Definition: Window.h:45
Memory group resources scope handling class.
Definition: IMemoryGroup.h:82
virtual size_t total_size() const =0
Returns the total size of the tensor in bytes.
virtual void schedule(ICPPKernel *kernel, const Hints &hints)=0
Runs the kernel in the same thread as the caller synchronously.
static constexpr size_t DimZ
Alias for dimension 2 also known as Z dimension.
Definition: Window.h:47
Class for specifying the size of an image or rectangle.
Definition: Size2D.h:34
#define ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(...)
Definition: Validate.h:545
Num samples, height, width, channels.
#define ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(t, c,...)
Definition: Validate.h:792
bool is_relu(ActivationLayerInfo activation_info)
Checks if activation information correspond to a relu activation function.
Definition: InfoHelpers.h:43
#define ARM_COMPUTE_ERROR_ON_NULLPTR(...)
Definition: Validate.h:161
Store the tensor&#39;s metadata.
Definition: TensorInfo.h:45
T y() const
Alias to access the size of the second dimension.
Definition: Dimensions.h:92
quantized, asymmetric fixed-point 8-bit number signed
virtual unsigned int num_threads() const =0
Returns the number of threads that the SingleThreadScheduler has in his pool.
size_t get_data_layout_dimension_index(const DataLayout data_layout, const DataLayoutDimension data_layout_dimension)
Get the index of the given dimension.
Definition: Helpers.inl:193
Status calculate_quantized_multiplier_less_than_one(float multiplier, int32_t *quant_multiplier, int32_t *right_shift, bool ignore_epsilon=false)
Calculate quantized representation of multiplier with value less than one.
void run() override
Run the kernels contained in the function.
unsigned int pad_bottom() const
Get the bottom padding.
Definition: Types.h:811
DataType
Available data types.
Definition: Types.h:77
unsigned int pad_left() const
Get the left padding.
Definition: Types.h:796
DataLayout
[DataLayout enum definition]
Definition: Types.h:120
signed 8-bit number
TensorShape & set(size_t dimension, size_t value, bool apply_dim_correction=true, bool increase_dim_unit=true)
Accessor to set the value of one of the dimensions.
Definition: TensorShape.h:79
bool is_data_type_float(DataType dt)
Check if a given data type is of floating point type.
Definition: Utils.h:1148
PadStrideInfo calculate_same_pad(TensorShape input_shape, TensorShape weights_shape, PadStrideInfo conv_info, DataLayout data_layout=DataLayout::NCHW, const Size2D &dilation=Size2D(1u, 1u), const DimensionRoundingType &rounding_type=DimensionRoundingType::FLOOR)
Calculate padding requirements in case of SAME padding.
Definition: Utils.cpp:357
virtual DataLayout data_layout() const =0
Get the data layout of the tensor.
static IScheduler & get()
Access the scheduler singleton.
Definition: Scheduler.cpp:94