24.04
a55r1.cpp
Go to the documentation of this file.
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/*
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* Copyright (c) 2017-2018 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef __arm__
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#include <arm_neon.h>
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#include "../../asmlib.hpp"
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// Kernel implementation.
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//
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// Assume that "Apanel" points to a chunk of A blocks (each size 6xK) in read-order.
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// Assume that "Bpanel" points to a chunk of B blocks (each size 8xK) in read-order.
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// Assume that "Cpanel" points to a chunk of C output blocks (each size
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// 8x6), the chunks being arranged in a row major fashion.
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//
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// Note that the intent of this is that either ablocks or bblocks will be 1
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// - this construction allows the output loop to proceed in either order.
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namespace
arm_gemm
{
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void
a32_sgemm_8x6_a55r1(
const
float
*Apanel,
const
float
*Bpanel,
float
*Cpanel,
int
ablocks,
int
bblocks,
int
K
) {
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const
float
*a_ptr = Apanel;
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float
*c_ptr = Cpanel;
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/* Work out starting values for "k" and "tails" in the inner loop. */
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int
tails_initial = (
K
& 3);
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if
(tails_initial == 0) {
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tails_initial = 4;
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}
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int
k_initial = ((
K
+3)/4) - 1;
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for
(
int
yb=0; yb<ablocks; yb++) {
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const
float
*a_ptr0 = a_ptr;
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const
float
*b_ptr = Bpanel;
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for
(
int
xb=0; xb<bblocks; xb++) {
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int
tails = tails_initial;
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int
k = k_initial;
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a_ptr = a_ptr0;
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__asm __volatile (
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"vldr d0, [%[a_ptr]]\n"
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"vmov.i32 q4, #0\n"
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"vldr d1, [%[a_ptr], #0x08]\n"
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"vmov.i32 q5, #0\n"
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"vldr d4, [%[b_ptr]]\n"
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"vmov.i32 q6, #0\n"
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"vldr d5, [%[b_ptr], #0x08]\n"
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"vmov.i32 q7, #0\n"
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"vldr d2, [%[a_ptr], #0x10]\n"
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"vmov.i32 q8, #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0x40]"
)
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"vmov.i32 q9, #0\n"
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ASM_PREFETCH
(
"[%[a_ptr], #0x40]"
)
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"vmov.i32 q10, #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0x80]"
)
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"vmov.i32 q11, #0\n"
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ASM_PREFETCH
(
"[%[a_ptr], #0x80]"
)
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"vmov.i32 q12, #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0XC0]"
)
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"vmov.i32 q13, #0\n"
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ASM_PREFETCH
(
"[%[a_ptr], #0xC0]"
)
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"vmov.i32 q14, #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0x100]"
)
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"vmov.i32 q15, #0\n"
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ASM_PREFETCH
(
"[%[a_ptr], #0x100]"
)
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"cmp %[k], #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0x140]"
)
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"beq 6f\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0x180]"
)
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"1:\n"
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// Unroll 0
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"vmla.f32 q4, q2, d0[0]\n"
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"vldr d6, [%[b_ptr], #0x10]\n"
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"vmla.f32 q5, q2, d0[1]\n"
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"vldr d7, [%[b_ptr], #0x18]\n"
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"vmla.f32 q6, q2, d1[0]\n"
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"vldr d3, [%[a_ptr], #0x18]\n"
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"vmla.f32 q7, q2, d1[1]\n"
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ASM_PREFETCH
(
"[%[a_ptr], #0x140]"
)
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"vmla.f32 q8, q2, d2[0]\n"
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"subs %[k], %[k], #1\n"
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"vmla.f32 q9, q2, d2[1]\n"
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"vldr d4, [%[b_ptr], #0x20]\n"
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"vmla.f32 q10, q3, d0[0]\n"
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"vldr d5, [%[b_ptr], #0x28]\n"
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"vmla.f32 q11, q3, d0[1]\n"
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"vldr d0, [%[a_ptr], #0x20]\n"
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"vmla.f32 q12, q3, d1[0]\n"
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"vmla.f32 q13, q3, d1[1]\n"
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"vldr d1, [%[a_ptr], #0x28]\n"
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"vmla.f32 q14, q3, d2[0]\n"
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"vmla.f32 q15, q3, d2[1]\n"
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"vldr d6, [%[b_ptr], #0x30]\n"
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// Unroll 1
123
"vmla.f32 q4, q2, d3[0]\n"
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"vldr d7, [%[b_ptr], #0x38]\n"
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"vmla.f32 q5, q2, d3[1]\n"
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"vldr d2, [%[a_ptr], #0x30]\n"
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"vmla.f32 q6, q2, d0[0]\n"
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"vmla.f32 q7, q2, d0[1]\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0x1C0]"
)
131
"vmla.f32 q8, q2, d1[0]\n"
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133
"vmla.f32 q9, q2, d1[1]\n"
134
"vldr d4, [%[b_ptr], #0x40]\n"
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"vmla.f32 q10, q3, d3[0]\n"
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"vldr d5, [%[b_ptr], #0x48]\n"
137
"vmla.f32 q11, q3, d3[1]\n"
138
"vldr d3, [%[a_ptr], #0x38]\n"
139
"vmla.f32 q12, q3, d0[0]\n"
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141
"vmla.f32 q13, q3, d0[1]\n"
142
"vldr d0, [%[a_ptr], #0x40]\n"
143
"vmla.f32 q14, q3, d1[0]\n"
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"vmla.f32 q15, q3, d1[1]\n"
146
"vldr d6, [%[b_ptr], #0x50]\n"
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148
// Unroll 2
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"vmla.f32 q4, q2, d2[0]\n"
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"vldr d7, [%[b_ptr], #0x58]\n"
151
"vmla.f32 q5, q2, d2[1]\n"
152
"vldr d1, [%[a_ptr], #0x48]\n"
153
"vmla.f32 q6, q2, d3[0]\n"
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155
"vmla.f32 q7, q2, d3[1]\n"
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ASM_PREFETCH
(
"[%[a_ptr], #0x180]"
)
157
"vmla.f32 q8, q2, d0[0]\n"
158
159
"vmla.f32 q9, q2, d0[1]\n"
160
"vldr d4, [%[b_ptr], #0x60]\n"
161
"vmla.f32 q10, q3, d2[0]\n"
162
"vldr d5, [%[b_ptr], #0x68]\n"
163
"vmla.f32 q11, q3, d2[1]\n"
164
"vldr d2, [%[a_ptr], #0x50]\n"
165
"vmla.f32 q12, q3, d3[0]\n"
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167
"vmla.f32 q13, q3, d3[1]\n"
168
"vldr d3, [%[a_ptr], #0x58]\n"
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"vmla.f32 q14, q3, d0[0]\n"
170
"add %[a_ptr], %[a_ptr], #0x60\n"
171
"vmla.f32 q15, q3, d0[1]\n"
172
"vldr d6, [%[b_ptr], #0x70]\n"
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174
// Unroll 3
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"vmla.f32 q4, q2, d1[0]\n"
176
"vldr d7, [%[b_ptr], #0x78]\n"
177
"vmla.f32 q5, q2, d1[1]\n"
178
"add %[b_ptr], %[b_ptr], #0x80\n"
179
"vmla.f32 q6, q2, d2[0]\n"
180
"vldr d0, [%[a_ptr], #0x00]\n"
181
"vmla.f32 q7, q2, d2[1]\n"
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ASM_PREFETCH
(
"[%[b_ptr], #0x180]"
)
183
"vmla.f32 q8, q2, d3[0]\n"
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"vmla.f32 q9, q2, d3[1]\n"
186
"vldr d4, [%[b_ptr], #0x00]\n"
187
"vmla.f32 q10, q3, d1[0]\n"
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"vldr d5, [%[b_ptr], #0x08]\n"
189
"vmla.f32 q11, q3, d1[1]\n"
190
"vldr d1, [%[a_ptr], #0x08]\n"
191
"vmla.f32 q12, q3, d2[0]\n"
192
193
"vmla.f32 q13, q3, d2[1]\n"
194
"vldr d2, [%[a_ptr], #0x10]\n"
195
"vmla.f32 q14, q3, d3[0]\n"
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197
"vmla.f32 q15, q3, d3[1]\n"
198
"bne 1b\n"
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200
// "Tails" shows how many multiply blocks are needed at the
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// end, must be 1-4 inclusive. Bail out to alternative tail
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// immediately if it's 1.
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"6:\n"
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"subs %[tails], %[tails], #1\n"
205
"beq 3f\n"
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207
// Detached final iteration
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209
// Unroll 0
210
"vmla.f32 q4, q2, d0[0]\n"
211
"vldr d6, [%[b_ptr], #0x10]\n"
212
"vmla.f32 q5, q2, d0[1]\n"
213
"vldr d7, [%[b_ptr], #0x18]\n"
214
"vmla.f32 q6, q2, d1[0]\n"
215
"vldr d3, [%[a_ptr], #0x18]\n"
216
"vmla.f32 q7, q2, d1[1]\n"
217
"subs %[tails], %[tails], #1\n"
218
"vmla.f32 q8, q2, d2[0]\n"
219
"vmla.f32 q9, q2, d2[1]\n"
220
"vldr d4, [%[b_ptr], #0x20]\n"
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222
"vmla.f32 q10, q3, d0[0]\n"
223
"vldr d5, [%[b_ptr], #0x28]\n"
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"vmla.f32 q11, q3, d0[1]\n"
225
"vldr d0, [%[a_ptr], #0x20]\n"
226
"vmla.f32 q12, q3, d1[0]\n"
227
"vmla.f32 q13, q3, d1[1]\n"
228
"vldr d1, [%[a_ptr], #0x28]\n"
229
"vmla.f32 q14, q3, d2[0]\n"
230
"vmla.f32 q15, q3, d2[1]\n"
231
"beq 4f\n"
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// Unroll 1
234
"vmla.f32 q4, q2, d3[0]\n"
235
"vldr d6, [%[b_ptr], #0x30]\n"
236
"vmla.f32 q5, q2, d3[1]\n"
237
"vldr d7, [%[b_ptr], #0x38]\n"
238
"vmla.f32 q6, q2, d0[0]\n"
239
"vldr d2, [%[a_ptr], #0x30]\n"
240
"vmla.f32 q7, q2, d0[1]\n"
241
"subs %[tails], %[tails], #1\n"
242
"vmla.f32 q8, q2, d1[0]\n"
243
244
"vmla.f32 q9, q2, d1[1]\n"
245
246
"vmla.f32 q10, q3, d3[0]\n"
247
"vldr d4, [%[b_ptr], #0x40]\n"
248
"vmla.f32 q11, q3, d3[1]\n"
249
"vldr d5, [%[b_ptr], #0x48]\n"
250
"vmla.f32 q12, q3, d0[0]\n"
251
"vldr d3, [%[a_ptr], #0x38]\n"
252
"vmla.f32 q13, q3, d0[1]\n"
253
"vldr d0, [%[a_ptr], #0x40]\n"
254
"vmla.f32 q14, q3, d1[0]\n"
255
"vmla.f32 q15, q3, d1[1]\n"
256
"beq 5f\n"
257
258
// Unroll 2
259
"vmla.f32 q4, q2, d2[0]\n"
260
"vldr d6, [%[b_ptr], #0x50]\n"
261
"vmla.f32 q5, q2, d2[1]\n"
262
"vldr d7, [%[b_ptr], #0x58]\n"
263
"vmla.f32 q6, q2, d3[0]\n"
264
"vldr d1, [%[a_ptr], #0x48]\n"
265
"vmla.f32 q7, q2, d3[1]\n"
266
"vmla.f32 q8, q2, d0[0]\n"
267
"vmla.f32 q9, q2, d0[1]\n"
268
269
"vmla.f32 q10, q3, d2[0]\n"
270
"vldr d4, [%[b_ptr], #0x60]\n"
271
"vmla.f32 q11, q3, d2[1]\n"
272
"vldr d5, [%[b_ptr], #0x68]\n"
273
"vmla.f32 q12, q3, d3[0]\n"
274
"vldr d2, [%[a_ptr], #0x50]\n"
275
"vmla.f32 q13, q3, d3[1]\n"
276
"vldr d3, [%[a_ptr], #0x58]\n"
277
"vmla.f32 q14, q3, d0[0]\n"
278
"vmla.f32 q15, q3, d0[1]\n"
279
280
// Unroll 3
281
"vmla.f32 q4, q2, d1[0]\n"
282
"vldr d6, [%[b_ptr], #0x70]\n"
283
"vmla.f32 q5, q2, d1[1]\n"
284
"vldr d7, [%[b_ptr], #0x78]\n"
285
"vmla.f32 q10, q3, d1[0]\n"
286
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
287
"vmla.f32 q11, q3, d1[1]\n"
288
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
289
"vmla.f32 q6, q2, d2[0]\n"
290
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
291
"vmla.f32 q12, q3, d2[0]\n"
292
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
293
"vmla.f32 q7, q2, d2[1]\n"
294
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
295
"vmla.f32 q13, q3, d2[1]\n"
296
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
297
"vmla.f32 q8, q2, d3[0]\n"
298
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
299
"vmla.f32 q14, q3, d3[0]\n"
300
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
301
"vmla.f32 q9, q2, d3[1]\n"
302
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
303
"vmla.f32 q15, q3, d3[1]\n"
304
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
305
"add %[a_ptr], %[a_ptr], #0x60\n"
306
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
307
"add %[b_ptr], %[b_ptr], #0x80\n"
308
"b 2f\n"
309
310
// tails==1 final tail
311
"3:\n"
312
"vmla.f32 q4, q2, d0[0]\n"
313
"vldr d6, [%[b_ptr], #0x10]\n"
314
"vmla.f32 q5, q2, d0[1]\n"
315
"vldr d7, [%[b_ptr], #0x18]\n"
316
"vmla.f32 q6, q2, d1[0]\n"
317
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
318
"vmla.f32 q10, q3, d0[0]\n"
319
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
320
"vmla.f32 q11, q3, d0[1]\n"
321
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
322
"vmla.f32 q12, q3, d1[0]\n"
323
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
324
"vmla.f32 q7, q2, d1[1]\n"
325
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
326
"vmla.f32 q13, q3, d1[1]\n"
327
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
328
"vmla.f32 q8, q2, d2[0]\n"
329
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
330
"vmla.f32 q14, q3, d2[0]\n"
331
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
332
"vmla.f32 q9, q2, d2[1]\n"
333
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
334
"vmla.f32 q15, q3, d2[1]\n"
335
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
336
"add %[a_ptr], %[a_ptr], #0x18\n"
337
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
338
"add %[b_ptr], %[b_ptr], #0x20\n"
339
"b 2f\n"
340
341
// tails==2 final tail
342
"4:\n"
343
"vmla.f32 q4, q2, d3[0]\n"
344
"vldr d6, [%[b_ptr], #0x30]\n"
345
"vmla.f32 q5, q2, d3[1]\n"
346
"vldr d7, [%[b_ptr], #0x38]\n"
347
"vmla.f32 q10, q3, d3[0]\n"
348
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
349
"vmla.f32 q11, q3, d3[1]\n"
350
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
351
"vmla.f32 q6, q2, d0[0]\n"
352
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
353
"vmla.f32 q12, q3, d0[0]\n"
354
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
355
"vmla.f32 q7, q2, d0[1]\n"
356
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
357
"vmla.f32 q13, q3, d0[1]\n"
358
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
359
"vmla.f32 q8, q2, d1[0]\n"
360
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
361
"vmla.f32 q14, q3, d1[0]\n"
362
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
363
"vmla.f32 q9, q2, d1[1]\n"
364
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
365
"vmla.f32 q15, q3, d1[1]\n"
366
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
367
"add %[b_ptr], %[b_ptr], #0x40\n"
368
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
369
"add %[a_ptr], %[a_ptr], #0x30\n"
370
"b 2f\n"
371
372
// tails==3 final tail
373
"5:\n"
374
"vmla.f32 q4, q2, d2[0]\n"
375
"vldr d6, [%[b_ptr], #0x50]\n"
376
"vmla.f32 q5, q2, d2[1]\n"
377
"vldr d7, [%[b_ptr], #0x58]\n"
378
"vmla.f32 q6, q2, d3[0]\n"
379
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
380
"vmla.f32 q10, q3, d2[0]\n"
381
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
382
"vmla.f32 q11, q3, d2[1]\n"
383
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
384
"vmla.f32 q12, q3, d3[0]\n"
385
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
386
"vmla.f32 q7, q2, d3[1]\n"
387
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
388
"vmla.f32 q13, q3, d3[1]\n"
389
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
390
"vmla.f32 q8, q2, d0[0]\n"
391
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
392
"vmla.f32 q14, q3, d0[0]\n"
393
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
394
"vmla.f32 q9, q2, d0[1]\n"
395
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
396
"vmla.f32 q15, q3, d0[1]\n"
397
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
398
"add %[a_ptr], %[a_ptr], #0x48\n"
399
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
400
"add %[b_ptr], %[b_ptr], #0x60\n"
401
402
"2:\n"
403
"vst1.32 {d30-d31}, [%[c_ptr] :128]!\n"
404
: [a_ptr]
"+r"
(a_ptr), [b_ptr]
"+r"
(b_ptr), [c_ptr]
"+r"
(c_ptr), [k]
"+r"
(k), [tails]
"+r"
(tails)
405
:
406
:
"q0"
,
"q1"
,
"q2"
,
"q3"
,
"q4"
,
"q5"
,
"q6"
,
"q7"
,
"q8"
,
"q9"
,
"q10"
,
"q11"
,
"q12"
,
"q13"
,
"q14"
,
"q15"
,
407
"r0"
,
"r1"
,
"cc"
,
"memory"
408
);
409
}
410
}
411
}
412
413
}
// namespace arm_gemm
414
415
#endif
ASM_PREFETCH
#define ASM_PREFETCH(address)
Definition:
asmlib.hpp:45
arm_gemm
Definition:
barrier.hpp:30
K
unsigned int K
Definition:
CpuGemmAssemblyDispatch.cpp:106
src
core
NEON
kernels
arm_gemm
kernels
a32_sgemm_8x6
a55r1.cpp
Generated on Mon Apr 29 2024 10:53:55 for Compute Library by
1.8.17