a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp

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/*
 * Copyright (c) 2021-2023 Arm Limited.
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#pragma once
 
#if defined(__aarch64__)
 
namespace arm_conv {
namespace pooling {
 
void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int);
 
struct a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float>
{
  using Parent = DepthfirstStrategy<float, float>;
 
  const static auto pooling_type = PoolingType::AVERAGE;
  const static auto pool_rows = 3u, pool_cols = 3u;
  const static auto stride_rows = 1u, stride_cols = 1u;
 
  a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *)
  : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {}
 
  Parent::KernelType get_kernel(void) const { return a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; }
};
 
}  // namespace pooling
}  // namespace arm_conv
 
#endif  // defined(__aarch64__)