24.04
a64_interleave4_block16_u8_u8_summing.hpp
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/*
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* Copyright (c) 2019-2021, 2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef __aarch64__
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template
<>
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void
interleave_block<4, 16, VLType::None, true>(
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uint8_t * &out_ptr,
const
uint8_t *
const
* in,
size_t
width,
size_t
height,
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size_t
row_offset,
bool
first
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)
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{
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__asm__ __volatile__(
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"ldr x24, [%x[in], #0x0]\n"
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"ldr x23, [%x[in], #0x8]\n"
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"cmp %x[height], #0x4\n"
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"mov x22, #0x0\n"
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"ldr x21, [%x[in], #0x10]\n"
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"ldr x20, [%x[in], #0x18]\n"
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"movi v28.8h, #0x0\n"
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"movi v27.8h, #0x0\n"
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"movi v26.8h, #0x0\n"
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"movi v25.8h, #0x0\n"
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"add x24, x24, %x[row_offset]\n"
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"add x23, x23, %x[row_offset]\n"
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"movi v24.4s, #0x0\n"
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"movi v23.4s, #0x0\n"
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"add x21, x21, %x[row_offset]\n"
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"add x20, x20, %x[row_offset]\n"
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"movi v22.4s, #0x0\n"
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"movi v21.4s, #0x0\n"
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"beq 1f\n"
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"cmp %x[height], #0x2\n"
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"mov x20, x24\n"
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"csel x23, x23, x24, GE\n"
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"csel x21, x21, x24, GT\n"
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"1:"
// no_pointer_adj
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"prfm pldl1keep, [x24, #0x0]\n"
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"prfm pldl1keep, [x23, #0x0]\n"
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"movi v20.4s, #0x0\n"
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"prfm pldl1keep, [x21, #0x0]\n"
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"prfm pldl1keep, [x20, #0x0]\n"
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"prfm pldl1keep, [x24, #0x40]\n"
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"prfm pldl1keep, [x23, #0x40]\n"
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"prfm pldl1keep, [x21, #0x40]\n"
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"prfm pldl1keep, [x20, #0x40]\n"
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"cbnz %w[first], 2f\n"
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"sub %x[out_ptr], %x[out_ptr], #0x10\n"
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"ld1 { v20.4s }, [%x[out_ptr]]\n"
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"2:"
// first_pass
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"cmp %x[width], #0x10\n"
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"blt 5f\n"
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"3:"
// Main loop head
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"cmp x22, #0x7e\n"
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"ble 4f\n"
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"uadalp v24.4s, v28.8h\n"
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"movi v28.8h, #0x0\n"
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"mov x22, #0x0\n"
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"uadalp v23.4s, v27.8h\n"
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"movi v27.8h, #0x0\n"
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"uadalp v22.4s, v26.8h\n"
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"movi v26.8h, #0x0\n"
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"uadalp v21.4s, v25.8h\n"
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"movi v25.8h, #0x0\n"
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"4:"
// no_accumulate_16
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"ldr q19, [x24], #0x10\n"
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"ldr q18, [x23], #0x10\n"
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"subs %x[width], %x[width], #0x10\n"
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"cmp %x[width], #0x10\n"
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"ldr q17, [x21], #0x10\n"
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"ldr q16, [x20], #0x10\n"
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"str q19, [%x[out_ptr], #0x0]\n"
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"uadalp v28.8h, v19.16b\n"
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"prfm pldl1keep, [x24, #0x70]\n"
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"prfm pldl1keep, [x23, #0x70]\n"
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"str q18, [%x[out_ptr], #0x10]\n"
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"uadalp v27.8h, v18.16b\n"
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"prfm pldl1keep, [x21, #0x70]\n"
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"prfm pldl1keep, [x20, #0x70]\n"
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"str q17, [%x[out_ptr], #0x20]\n"
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"uadalp v26.8h, v17.16b\n"
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"str q16, [%x[out_ptr], #0x30]\n"
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"uadalp v25.8h, v16.16b\n"
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"add x22, x22, #0x1\n"
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"add %x[out_ptr], %x[out_ptr], #0x40\n"
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"bge 3b\n"
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"5:"
// Main loop skip
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"cbz %x[width], 14f\n"
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"tbz %x[width], #3, 9f\n"
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"ldr d19, [x24], #0x8\n"
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"ldr d18, [x23], #0x8\n"
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"ldr d17, [x21], #0x8\n"
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"ldr d16, [x20], #0x8\n"
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"tbz %x[width], #2, 7f\n"
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"ld1 { v19.s }[2], [x24], #0x4\n"
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"ld1 { v18.s }[2], [x23], #0x4\n"
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"ld1 { v17.s }[2], [x21], #0x4\n"
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"ld1 { v16.s }[2], [x20], #0x4\n"
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"tbz %x[width], #1, 6f\n"
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"ld1 { v19.h }[6], [x24], #0x2\n"
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"ld1 { v18.h }[6], [x23], #0x2\n"
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"ld1 { v17.h }[6], [x21], #0x2\n"
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"ld1 { v16.h }[6], [x20], #0x2\n"
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"tbz %x[width], #0, 13f\n"
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"ld1 { v19.b }[14], [x24]\n"
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"ld1 { v18.b }[14], [x23]\n"
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"ld1 { v17.b }[14], [x21]\n"
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"ld1 { v16.b }[14], [x20]\n"
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"b 13f\n"
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"6:"
// odd_loads_1_12
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"tbz %x[width], #0, 13f\n"
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"ld1 { v19.b }[12], [x24]\n"
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"ld1 { v18.b }[12], [x23]\n"
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"ld1 { v17.b }[12], [x21]\n"
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"ld1 { v16.b }[12], [x20]\n"
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"b 13f\n"
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"7:"
// odd_loads_2_8
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"tbz %x[width], #1, 8f\n"
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"ld1 { v19.h }[4], [x24], #0x2\n"
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"ld1 { v18.h }[4], [x23], #0x2\n"
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"ld1 { v17.h }[4], [x21], #0x2\n"
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"ld1 { v16.h }[4], [x20], #0x2\n"
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"tbz %x[width], #0, 13f\n"
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"ld1 { v19.b }[10], [x24]\n"
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"ld1 { v18.b }[10], [x23]\n"
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"ld1 { v17.b }[10], [x21]\n"
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"ld1 { v16.b }[10], [x20]\n"
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"b 13f\n"
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"8:"
// odd_loads_1_8
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"tbz %x[width], #0, 13f\n"
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"ld1 { v19.b }[8], [x24]\n"
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"ld1 { v18.b }[8], [x23]\n"
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"ld1 { v17.b }[8], [x21]\n"
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"ld1 { v16.b }[8], [x20]\n"
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"b 13f\n"
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"9:"
// odd_loads_4_0
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"tbz %x[width], #2, 11f\n"
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"ldr s19, [x24], #0x4\n"
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"ldr s18, [x23], #0x4\n"
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"ldr s17, [x21], #0x4\n"
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"ldr s16, [x20], #0x4\n"
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"tbz %x[width], #1, 10f\n"
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"ld1 { v19.h }[2], [x24], #0x2\n"
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"ld1 { v18.h }[2], [x23], #0x2\n"
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"ld1 { v17.h }[2], [x21], #0x2\n"
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"ld1 { v16.h }[2], [x20], #0x2\n"
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"tbz %x[width], #0, 13f\n"
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"ld1 { v19.b }[6], [x24]\n"
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"ld1 { v18.b }[6], [x23]\n"
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"ld1 { v17.b }[6], [x21]\n"
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"ld1 { v16.b }[6], [x20]\n"
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"b 13f\n"
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"10:"
// odd_loads_1_4
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"tbz %x[width], #0, 13f\n"
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"ld1 { v19.b }[4], [x24]\n"
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"ld1 { v18.b }[4], [x23]\n"
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"ld1 { v17.b }[4], [x21]\n"
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"ld1 { v16.b }[4], [x20]\n"
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"b 13f\n"
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"11:"
// odd_loads_2_0
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"tbz %x[width], #1, 12f\n"
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"ldr h19, [x24], #0x2\n"
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"ldr h18, [x23], #0x2\n"
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"ldr h17, [x21], #0x2\n"
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"ldr h16, [x20], #0x2\n"
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"tbz %x[width], #0, 13f\n"
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"ld1 { v19.b }[2], [x24]\n"
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"ld1 { v18.b }[2], [x23]\n"
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"ld1 { v17.b }[2], [x21]\n"
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"ld1 { v16.b }[2], [x20]\n"
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"b 13f\n"
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"12:"
// odd_loads_1_0
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"ldr b19, [x24, #0x0]\n"
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"ldr b18, [x23, #0x0]\n"
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"ldr b17, [x21, #0x0]\n"
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"ldr b16, [x20, #0x0]\n"
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"13:"
// Odd load end
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"str q19, [%x[out_ptr], #0x0]\n"
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"uadalp v28.8h, v19.16b\n"
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"uadalp v27.8h, v18.16b\n"
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"str q18, [%x[out_ptr], #0x10]\n"
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"uadalp v26.8h, v17.16b\n"
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"uadalp v25.8h, v16.16b\n"
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"str q17, [%x[out_ptr], #0x20]\n"
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"str q16, [%x[out_ptr], #0x30]\n"
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"add %x[out_ptr], %x[out_ptr], #0x40\n"
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"14:"
// Odds skip
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"uadalp v24.4s, v28.8h\n"
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"uadalp v23.4s, v27.8h\n"
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"uadalp v22.4s, v26.8h\n"
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"uadalp v21.4s, v25.8h\n"
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"addp v24.4s, v24.4s, v23.4s\n"
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"addp v16.4s, v22.4s, v21.4s\n"
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"addp v24.4s, v24.4s, v16.4s\n"
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"add v24.4s, v24.4s, v20.4s\n"
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"str q24, [%x[out_ptr], #0x0]\n"
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"add %x[out_ptr], %x[out_ptr], #0x10\n"
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: [out_ptr]
"+&r"
(out_ptr), [width]
"+&r"
(width)
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: [first]
"r"
(first), [height]
"r"
(height), [in]
"r"
(in), [row_offset]
"r"
(row_offset)
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:
"cc"
,
"memory"
,
"v16"
,
"v17"
,
"v18"
,
"v19"
,
"v20"
,
"v21"
,
"v22"
,
"v23"
,
"v24"
,
"v25"
,
"v26"
,
"v27"
,
"v28"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"x24"
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);
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}
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#endif // __aarch64__
src
core
NEON
kernels
arm_gemm
indirect-interleaves
a64_interleave4_block16_u8_u8_summing.hpp
Generated on Mon Apr 29 2024 10:53:55 for Compute Library by
1.8.17