24.04
a64_interleave8_block1_s16_s16.hpp
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2019-2021, 2023 Arm Limited.
3
*
4
* SPDX-License-Identifier: MIT
5
*
6
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
* of this software and associated documentation files (the "Software"), to
8
* deal in the Software without restriction, including without limitation the
9
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10
* sell copies of the Software, and to permit persons to whom the Software is
11
* furnished to do so, subject to the following conditions:
12
*
13
* The above copyright notice and this permission notice shall be included in all
14
* copies or substantial portions of the Software.
15
*
16
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22
* SOFTWARE.
23
*/
24
25
#ifdef __aarch64__
26
27
template
<>
28
void
interleave_block<8, 1, VLType::None, false>(
29
int16_t * &out_ptr,
const
int16_t *
const
* in,
size_t
width,
size_t
height,
30
size_t
row_offset,
bool
31
)
32
{
33
__asm__ __volatile__(
34
"ldr x28, [%x[in], #0x0]\n"
35
"ldr x27, [%x[in], #0x8]\n"
36
"cmp %x[height], #0x8\n"
37
"add x28, x28, %x[row_offset], LSL #1\n"
38
"ldr x26, [%x[in], #0x10]\n"
39
"ldr x25, [%x[in], #0x18]\n"
40
"add x27, x27, %x[row_offset], LSL #1\n"
41
"add x26, x26, %x[row_offset], LSL #1\n"
42
"ldr x24, [%x[in], #0x20]\n"
43
"ldr x23, [%x[in], #0x28]\n"
44
"add x25, x25, %x[row_offset], LSL #1\n"
45
"add x24, x24, %x[row_offset], LSL #1\n"
46
"ldr x22, [%x[in], #0x30]\n"
47
"ldr x21, [%x[in], #0x38]\n"
48
"add x23, x23, %x[row_offset], LSL #1\n"
49
"add x22, x22, %x[row_offset], LSL #1\n"
50
"add x21, x21, %x[row_offset], LSL #1\n"
51
"beq 1f\n"
52
"cmp %x[height], #0x2\n"
53
"csel x27, x27, x28, GE\n"
54
"csel x26, x26, x28, GT\n"
55
"cmp %x[height], #0x4\n"
56
"csel x25, x25, x28, GE\n"
57
"csel x24, x24, x28, GT\n"
58
"cmp %x[height], #0x6\n"
59
"mov x21, x28\n"
60
"csel x23, x23, x28, GE\n"
61
"csel x22, x22, x28, GT\n"
62
"1:"
// no_pointer_adj
63
"cmp %x[width], #0x8\n"
64
"prfm pldl1keep, [x28, #0x0]\n"
65
"prfm pldl1keep, [x27, #0x0]\n"
66
"prfm pldl1keep, [x26, #0x0]\n"
67
"prfm pldl1keep, [x25, #0x0]\n"
68
"prfm pldl1keep, [x24, #0x0]\n"
69
"prfm pldl1keep, [x23, #0x0]\n"
70
"prfm pldl1keep, [x22, #0x0]\n"
71
"prfm pldl1keep, [x21, #0x0]\n"
72
"prfm pldl1keep, [x28, #0x40]\n"
73
"prfm pldl1keep, [x27, #0x40]\n"
74
"prfm pldl1keep, [x26, #0x40]\n"
75
"prfm pldl1keep, [x25, #0x40]\n"
76
"prfm pldl1keep, [x24, #0x40]\n"
77
"prfm pldl1keep, [x23, #0x40]\n"
78
"prfm pldl1keep, [x22, #0x40]\n"
79
"prfm pldl1keep, [x21, #0x40]\n"
80
"blt 3f\n"
81
"2:"
// Main loop head
82
"ldr q25, [x28], #0x10\n"
83
"ldr q27, [x27], #0x10\n"
84
"subs %x[width], %x[width], #0x8\n"
85
"cmp %x[width], #0x8\n"
86
"ldr q26, [x26], #0x10\n"
87
"ldr q24, [x25], #0x10\n"
88
"ldr q21, [x24], #0x10\n"
89
"ldr q20, [x23], #0x10\n"
90
"zip1 v23.8h, v25.8h, v21.8h\n"
91
"zip1 v22.8h, v27.8h, v20.8h\n"
92
"ldr q17, [x22], #0x10\n"
93
"ldr q16, [x21], #0x10\n"
94
"zip1 v19.8h, v26.8h, v17.8h\n"
95
"zip1 v18.8h, v24.8h, v16.8h\n"
96
"zip2 v25.8h, v25.8h, v21.8h\n"
97
"zip2 v21.8h, v26.8h, v17.8h\n"
98
"prfm pldl1keep, [x28, #0x70]\n"
99
"prfm pldl1keep, [x27, #0x70]\n"
100
"zip2 v20.8h, v27.8h, v20.8h\n"
101
"zip2 v16.8h, v24.8h, v16.8h\n"
102
"prfm pldl1keep, [x26, #0x70]\n"
103
"prfm pldl1keep, [x25, #0x70]\n"
104
"zip1 v24.8h, v23.8h, v19.8h\n"
105
"zip1 v17.8h, v22.8h, v18.8h\n"
106
"prfm pldl1keep, [x24, #0x70]\n"
107
"prfm pldl1keep, [x23, #0x70]\n"
108
"zip2 v23.8h, v23.8h, v19.8h\n"
109
"zip2 v19.8h, v22.8h, v18.8h\n"
110
"prfm pldl1keep, [x22, #0x70]\n"
111
"prfm pldl1keep, [x21, #0x70]\n"
112
"zip1 v22.8h, v25.8h, v21.8h\n"
113
"zip1 v18.8h, v20.8h, v16.8h\n"
114
"zip2 v21.8h, v25.8h, v21.8h\n"
115
"zip2 v20.8h, v20.8h, v16.8h\n"
116
"zip1 v16.8h, v24.8h, v17.8h\n"
117
"str q16, [%x[out_ptr], #0x0]\n"
118
"zip2 v16.8h, v24.8h, v17.8h\n"
119
"str q16, [%x[out_ptr], #0x10]\n"
120
"zip1 v17.8h, v23.8h, v19.8h\n"
121
"zip2 v16.8h, v23.8h, v19.8h\n"
122
"str q17, [%x[out_ptr], #0x20]\n"
123
"zip1 v19.8h, v22.8h, v18.8h\n"
124
"zip2 v18.8h, v22.8h, v18.8h\n"
125
"str q16, [%x[out_ptr], #0x30]\n"
126
"zip1 v17.8h, v21.8h, v20.8h\n"
127
"zip2 v16.8h, v21.8h, v20.8h\n"
128
"str q19, [%x[out_ptr], #0x40]\n"
129
"str q18, [%x[out_ptr], #0x50]\n"
130
"str q17, [%x[out_ptr], #0x60]\n"
131
"str q16, [%x[out_ptr], #0x70]\n"
132
"add %x[out_ptr], %x[out_ptr], #0x80\n"
133
"bge 2b\n"
134
"3:"
// Main loop skip
135
"cbz %x[width], 8f\n"
136
"tbz %x[width], #2, 5f\n"
137
"ldr d30, [x28], #0x8\n"
138
"ldr d29, [x27], #0x8\n"
139
"ldr d28, [x26], #0x8\n"
140
"ldr d27, [x25], #0x8\n"
141
"ldr d26, [x24], #0x8\n"
142
"ldr d25, [x23], #0x8\n"
143
"ldr d24, [x22], #0x8\n"
144
"ldr d23, [x21], #0x8\n"
145
"tbz %x[width], #1, 4f\n"
146
"ld1 { v30.s }[2], [x28], #0x4\n"
147
"ld1 { v29.s }[2], [x27], #0x4\n"
148
"mov x20, #0x6\n"
149
"ld1 { v28.s }[2], [x26], #0x4\n"
150
"ld1 { v27.s }[2], [x25], #0x4\n"
151
"ld1 { v26.s }[2], [x24], #0x4\n"
152
"ld1 { v25.s }[2], [x23], #0x4\n"
153
"ld1 { v24.s }[2], [x22], #0x4\n"
154
"ld1 { v23.s }[2], [x21], #0x4\n"
155
"tbz %x[width], #0, 7f\n"
156
"ld1 { v30.h }[6], [x28]\n"
157
"ld1 { v29.h }[6], [x27]\n"
158
"mov x20, #0x7\n"
159
"ld1 { v28.h }[6], [x26]\n"
160
"ld1 { v27.h }[6], [x25]\n"
161
"ld1 { v26.h }[6], [x24]\n"
162
"ld1 { v25.h }[6], [x23]\n"
163
"ld1 { v24.h }[6], [x22]\n"
164
"ld1 { v23.h }[6], [x21]\n"
165
"b 7f\n"
166
"4:"
// odd_loads_1_4
167
"mov x20, #0x4\n"
168
"tbz %x[width], #0, 7f\n"
169
"ld1 { v30.h }[4], [x28]\n"
170
"ld1 { v29.h }[4], [x27]\n"
171
"mov x20, #0x5\n"
172
"ld1 { v28.h }[4], [x26]\n"
173
"ld1 { v27.h }[4], [x25]\n"
174
"ld1 { v26.h }[4], [x24]\n"
175
"ld1 { v25.h }[4], [x23]\n"
176
"ld1 { v24.h }[4], [x22]\n"
177
"ld1 { v23.h }[4], [x21]\n"
178
"b 7f\n"
179
"5:"
// odd_loads_2_0
180
"tbz %x[width], #1, 6f\n"
181
"ldr s30, [x28], #0x4\n"
182
"ldr s29, [x27], #0x4\n"
183
"mov x20, #0x2\n"
184
"ldr s28, [x26], #0x4\n"
185
"ldr s27, [x25], #0x4\n"
186
"ldr s26, [x24], #0x4\n"
187
"ldr s25, [x23], #0x4\n"
188
"ldr s24, [x22], #0x4\n"
189
"ldr s23, [x21], #0x4\n"
190
"tbz %x[width], #0, 7f\n"
191
"ld1 { v30.h }[2], [x28]\n"
192
"ld1 { v29.h }[2], [x27]\n"
193
"mov x20, #0x3\n"
194
"ld1 { v28.h }[2], [x26]\n"
195
"ld1 { v27.h }[2], [x25]\n"
196
"ld1 { v26.h }[2], [x24]\n"
197
"ld1 { v25.h }[2], [x23]\n"
198
"ld1 { v24.h }[2], [x22]\n"
199
"ld1 { v23.h }[2], [x21]\n"
200
"b 7f\n"
201
"6:"
// odd_loads_1_0
202
"ldr h30, [x28, #0x0]\n"
203
"ldr h29, [x27, #0x0]\n"
204
"mov x20, #0x1\n"
205
"ldr h28, [x26, #0x0]\n"
206
"ldr h27, [x25, #0x0]\n"
207
"ldr h26, [x24, #0x0]\n"
208
"ldr h25, [x23, #0x0]\n"
209
"ldr h24, [x22, #0x0]\n"
210
"ldr h23, [x21, #0x0]\n"
211
"7:"
// Odd load end
212
"zip1 v22.8h, v30.8h, v26.8h\n"
213
"zip1 v21.8h, v28.8h, v24.8h\n"
214
"subs x20, x20, #0x1\n"
215
"zip1 v20.8h, v29.8h, v25.8h\n"
216
"zip1 v19.8h, v27.8h, v23.8h\n"
217
"zip1 v18.8h, v22.8h, v21.8h\n"
218
"zip1 v17.8h, v20.8h, v19.8h\n"
219
"zip1 v16.8h, v18.8h, v17.8h\n"
220
"str q16, [%x[out_ptr], #0x0]\n"
221
"add %x[out_ptr], %x[out_ptr], #0x10\n"
222
"beq 8f\n"
223
"subs x20, x20, #0x1\n"
224
"zip2 v16.8h, v18.8h, v17.8h\n"
225
"str q16, [%x[out_ptr], #0x0]\n"
226
"add %x[out_ptr], %x[out_ptr], #0x10\n"
227
"beq 8f\n"
228
"zip2 v18.8h, v22.8h, v21.8h\n"
229
"zip2 v17.8h, v20.8h, v19.8h\n"
230
"subs x20, x20, #0x1\n"
231
"zip1 v16.8h, v18.8h, v17.8h\n"
232
"str q16, [%x[out_ptr], #0x0]\n"
233
"add %x[out_ptr], %x[out_ptr], #0x10\n"
234
"beq 8f\n"
235
"subs x20, x20, #0x1\n"
236
"zip2 v16.8h, v18.8h, v17.8h\n"
237
"str q16, [%x[out_ptr], #0x0]\n"
238
"add %x[out_ptr], %x[out_ptr], #0x10\n"
239
"beq 8f\n"
240
"zip2 v22.8h, v30.8h, v26.8h\n"
241
"zip2 v21.8h, v28.8h, v24.8h\n"
242
"subs x20, x20, #0x1\n"
243
"zip2 v20.8h, v29.8h, v25.8h\n"
244
"zip2 v19.8h, v27.8h, v23.8h\n"
245
"zip1 v18.8h, v22.8h, v21.8h\n"
246
"zip1 v17.8h, v20.8h, v19.8h\n"
247
"zip1 v16.8h, v18.8h, v17.8h\n"
248
"str q16, [%x[out_ptr], #0x0]\n"
249
"add %x[out_ptr], %x[out_ptr], #0x10\n"
250
"beq 8f\n"
251
"subs x20, x20, #0x1\n"
252
"zip2 v16.8h, v18.8h, v17.8h\n"
253
"str q16, [%x[out_ptr], #0x0]\n"
254
"add %x[out_ptr], %x[out_ptr], #0x10\n"
255
"beq 8f\n"
256
"zip2 v17.8h, v22.8h, v21.8h\n"
257
"zip2 v16.8h, v20.8h, v19.8h\n"
258
"zip1 v16.8h, v17.8h, v16.8h\n"
259
"str q16, [%x[out_ptr], #0x0]\n"
260
"add %x[out_ptr], %x[out_ptr], #0x10\n"
261
"8:"
// Odds skip
262
: [out_ptr]
"+&r"
(out_ptr), [width]
"+&r"
(width)
263
: [height]
"r"
(height), [in]
"r"
(in), [row_offset]
"r"
(row_offset)
264
:
"cc"
,
"memory"
,
"v16"
,
"v17"
,
"v18"
,
"v19"
,
"v20"
,
"v21"
,
"v22"
,
"v23"
,
"v24"
,
"v25"
,
"v26"
,
"v27"
,
"v28"
,
"v29"
,
"v30"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"x24"
,
"x25"
,
"x26"
,
"x27"
,
"x28"
265
);
266
}
267
268
template
<>
269
void
interleave_block<8, 1, VLType::None, false>(
270
uint16_t * &out_ptr,
const
uint16_t *
const
* in,
size_t
width,
size_t
height,
271
size_t
row_offset,
bool
272
)
273
{
274
int16_t * &out_cast =
reinterpret_cast<
int16_t * &
>
(out_ptr);
275
const
int16_t *
const
* in_cast =
reinterpret_cast<
const
int16_t *
const
*
>
(in);
276
277
interleave_block<8, 1, VLType::None, false>(out_cast, in_cast, width, height, row_offset,
false
);
278
}
279
280
281
#endif // __aarch64__
src
core
NEON
kernels
arm_gemm
indirect-interleaves
a64_interleave8_block1_s16_s16.hpp
Generated on Mon Apr 29 2024 10:53:55 for Compute Library by
1.8.17