24.04
a64_interleave8_block1_u8_u16.hpp
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/*
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* Copyright (c) 2019-2021, 2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef __aarch64__
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template
<>
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void
interleave_block<8, 1, VLType::None, false>(
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uint16_t * &out_ptr,
const
uint8_t *
const
* in,
size_t
width,
size_t
height,
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size_t
row_offset,
bool
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)
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{
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__asm__ __volatile__(
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"ldr x28, [%x[in], #0x0]\n"
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"ldr x27, [%x[in], #0x8]\n"
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"cmp %x[height], #0x8\n"
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"add x28, x28, %x[row_offset]\n"
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"ldr x26, [%x[in], #0x10]\n"
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"ldr x25, [%x[in], #0x18]\n"
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"add x27, x27, %x[row_offset]\n"
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"add x26, x26, %x[row_offset]\n"
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"ldr x24, [%x[in], #0x20]\n"
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"ldr x23, [%x[in], #0x28]\n"
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"add x25, x25, %x[row_offset]\n"
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"add x24, x24, %x[row_offset]\n"
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"ldr x22, [%x[in], #0x30]\n"
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"ldr x21, [%x[in], #0x38]\n"
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"add x23, x23, %x[row_offset]\n"
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"add x22, x22, %x[row_offset]\n"
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"add x21, x21, %x[row_offset]\n"
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"beq 1f\n"
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"cmp %x[height], #0x2\n"
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"csel x27, x27, x28, GE\n"
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"csel x26, x26, x28, GT\n"
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"cmp %x[height], #0x4\n"
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"csel x25, x25, x28, GE\n"
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"csel x24, x24, x28, GT\n"
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"cmp %x[height], #0x6\n"
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"mov x21, x28\n"
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"csel x23, x23, x28, GE\n"
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"csel x22, x22, x28, GT\n"
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"1:"
// no_pointer_adj
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"cmp %x[width], #0x8\n"
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"prfm pldl1keep, [x28, #0x0]\n"
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"prfm pldl1keep, [x27, #0x0]\n"
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"prfm pldl1keep, [x26, #0x0]\n"
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"prfm pldl1keep, [x25, #0x0]\n"
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"prfm pldl1keep, [x24, #0x0]\n"
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"prfm pldl1keep, [x23, #0x0]\n"
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"prfm pldl1keep, [x22, #0x0]\n"
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"prfm pldl1keep, [x21, #0x0]\n"
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"prfm pldl1keep, [x28, #0x40]\n"
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"prfm pldl1keep, [x27, #0x40]\n"
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"prfm pldl1keep, [x26, #0x40]\n"
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"prfm pldl1keep, [x25, #0x40]\n"
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"prfm pldl1keep, [x24, #0x40]\n"
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"prfm pldl1keep, [x23, #0x40]\n"
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"prfm pldl1keep, [x22, #0x40]\n"
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"prfm pldl1keep, [x21, #0x40]\n"
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"blt 3f\n"
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"2:"
// Main loop head
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"ldr d25, [x28], #0x8\n"
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"ldr d27, [x27], #0x8\n"
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"ushll v25.8h, v25.8b, #0x0\n"
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"ushll v27.8h, v27.8b, #0x0\n"
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"ldr d26, [x26], #0x8\n"
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"ldr d24, [x25], #0x8\n"
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"ushll v26.8h, v26.8b, #0x0\n"
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"ushll v24.8h, v24.8b, #0x0\n"
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"ldr d21, [x24], #0x8\n"
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"ldr d20, [x23], #0x8\n"
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"ushll v21.8h, v21.8b, #0x0\n"
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"ushll v20.8h, v20.8b, #0x0\n"
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"ldr d17, [x22], #0x8\n"
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"ldr d16, [x21], #0x8\n"
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"ushll v17.8h, v17.8b, #0x0\n"
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"ushll v16.8h, v16.8b, #0x0\n"
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"zip1 v23.8h, v25.8h, v21.8h\n"
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"zip1 v22.8h, v26.8h, v17.8h\n"
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"subs %x[width], %x[width], #0x8\n"
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"cmp %x[width], #0x8\n"
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"zip1 v19.8h, v27.8h, v20.8h\n"
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"zip1 v18.8h, v24.8h, v16.8h\n"
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"prfm pldl1keep, [x28, #0x70]\n"
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"prfm pldl1keep, [x27, #0x70]\n"
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"zip2 v25.8h, v25.8h, v21.8h\n"
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"zip2 v21.8h, v26.8h, v17.8h\n"
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"prfm pldl1keep, [x26, #0x70]\n"
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"prfm pldl1keep, [x25, #0x70]\n"
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"zip2 v20.8h, v27.8h, v20.8h\n"
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"zip2 v16.8h, v24.8h, v16.8h\n"
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"prfm pldl1keep, [x24, #0x70]\n"
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"prfm pldl1keep, [x23, #0x70]\n"
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"zip1 v24.8h, v23.8h, v22.8h\n"
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"zip1 v17.8h, v19.8h, v18.8h\n"
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"prfm pldl1keep, [x22, #0x70]\n"
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"prfm pldl1keep, [x21, #0x70]\n"
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"zip2 v23.8h, v23.8h, v22.8h\n"
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"zip2 v19.8h, v19.8h, v18.8h\n"
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"zip1 v22.8h, v25.8h, v21.8h\n"
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"zip1 v18.8h, v20.8h, v16.8h\n"
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"zip2 v21.8h, v25.8h, v21.8h\n"
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"zip2 v20.8h, v20.8h, v16.8h\n"
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"zip1 v16.8h, v24.8h, v17.8h\n"
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"str q16, [%x[out_ptr], #0x0]\n"
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"zip2 v16.8h, v24.8h, v17.8h\n"
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"str q16, [%x[out_ptr], #0x10]\n"
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"zip1 v17.8h, v23.8h, v19.8h\n"
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"zip2 v16.8h, v23.8h, v19.8h\n"
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"str q17, [%x[out_ptr], #0x20]\n"
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"zip1 v19.8h, v22.8h, v18.8h\n"
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"zip2 v18.8h, v22.8h, v18.8h\n"
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"str q16, [%x[out_ptr], #0x30]\n"
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"zip1 v17.8h, v21.8h, v20.8h\n"
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"zip2 v16.8h, v21.8h, v20.8h\n"
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"str q19, [%x[out_ptr], #0x40]\n"
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"str q18, [%x[out_ptr], #0x50]\n"
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"str q17, [%x[out_ptr], #0x60]\n"
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"str q16, [%x[out_ptr], #0x70]\n"
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"add %x[out_ptr], %x[out_ptr], #0x80\n"
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"bge 2b\n"
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"3:"
// Main loop skip
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"cbz %x[width], 8f\n"
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"tbz %x[width], #2, 5f\n"
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"ldr s30, [x28], #0x4\n"
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"ldr s29, [x27], #0x4\n"
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"ldr s28, [x26], #0x4\n"
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"ldr s27, [x25], #0x4\n"
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"ldr s26, [x24], #0x4\n"
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"ldr s25, [x23], #0x4\n"
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"ldr s24, [x22], #0x4\n"
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"ldr s23, [x21], #0x4\n"
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"tbz %x[width], #1, 4f\n"
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"ld1 { v30.h }[2], [x28], #0x2\n"
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"ld1 { v29.h }[2], [x27], #0x2\n"
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"mov x20, #0x6\n"
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"ld1 { v28.h }[2], [x26], #0x2\n"
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"ld1 { v27.h }[2], [x25], #0x2\n"
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"ld1 { v26.h }[2], [x24], #0x2\n"
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"ld1 { v25.h }[2], [x23], #0x2\n"
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"ld1 { v24.h }[2], [x22], #0x2\n"
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"ld1 { v23.h }[2], [x21], #0x2\n"
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"tbz %x[width], #0, 7f\n"
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"ld1 { v30.b }[6], [x28]\n"
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"ld1 { v29.b }[6], [x27]\n"
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"mov x20, #0x7\n"
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"ld1 { v28.b }[6], [x26]\n"
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"ld1 { v27.b }[6], [x25]\n"
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"ld1 { v26.b }[6], [x24]\n"
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"ld1 { v25.b }[6], [x23]\n"
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"ld1 { v24.b }[6], [x22]\n"
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"ld1 { v23.b }[6], [x21]\n"
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"b 7f\n"
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"4:"
// odd_loads_1_4
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"mov x20, #0x4\n"
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"tbz %x[width], #0, 7f\n"
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"ld1 { v30.b }[4], [x28]\n"
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"ld1 { v29.b }[4], [x27]\n"
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"mov x20, #0x5\n"
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"ld1 { v28.b }[4], [x26]\n"
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"ld1 { v27.b }[4], [x25]\n"
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"ld1 { v26.b }[4], [x24]\n"
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"ld1 { v25.b }[4], [x23]\n"
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"ld1 { v24.b }[4], [x22]\n"
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"ld1 { v23.b }[4], [x21]\n"
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"b 7f\n"
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"5:"
// odd_loads_2_0
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"tbz %x[width], #1, 6f\n"
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"ldr h30, [x28], #0x2\n"
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"ldr h29, [x27], #0x2\n"
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"mov x20, #0x2\n"
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"ldr h28, [x26], #0x2\n"
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"ldr h27, [x25], #0x2\n"
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"ldr h26, [x24], #0x2\n"
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"ldr h25, [x23], #0x2\n"
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"ldr h24, [x22], #0x2\n"
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"ldr h23, [x21], #0x2\n"
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"tbz %x[width], #0, 7f\n"
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"ld1 { v30.b }[2], [x28]\n"
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"ld1 { v29.b }[2], [x27]\n"
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"mov x20, #0x3\n"
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"ld1 { v28.b }[2], [x26]\n"
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"ld1 { v27.b }[2], [x25]\n"
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"ld1 { v26.b }[2], [x24]\n"
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"ld1 { v25.b }[2], [x23]\n"
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"ld1 { v24.b }[2], [x22]\n"
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"ld1 { v23.b }[2], [x21]\n"
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"b 7f\n"
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"6:"
// odd_loads_1_0
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"ldr b30, [x28, #0x0]\n"
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"ldr b29, [x27, #0x0]\n"
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"mov x20, #0x1\n"
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"ldr b28, [x26, #0x0]\n"
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"ldr b27, [x25, #0x0]\n"
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"ldr b26, [x24, #0x0]\n"
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"ldr b25, [x23, #0x0]\n"
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"ldr b24, [x22, #0x0]\n"
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"ldr b23, [x21, #0x0]\n"
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"7:"
// Odd load end
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"ushll v30.8h, v30.8b, #0x0\n"
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"ushll v29.8h, v29.8b, #0x0\n"
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"subs x20, x20, #0x1\n"
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"ushll v28.8h, v28.8b, #0x0\n"
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"ushll v27.8h, v27.8b, #0x0\n"
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"ushll v26.8h, v26.8b, #0x0\n"
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"ushll v25.8h, v25.8b, #0x0\n"
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"ushll v24.8h, v24.8b, #0x0\n"
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"ushll v23.8h, v23.8b, #0x0\n"
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"zip1 v22.8h, v30.8h, v26.8h\n"
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"zip1 v21.8h, v28.8h, v24.8h\n"
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"zip1 v20.8h, v29.8h, v25.8h\n"
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"zip1 v19.8h, v27.8h, v23.8h\n"
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"zip1 v18.8h, v22.8h, v21.8h\n"
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"zip1 v17.8h, v20.8h, v19.8h\n"
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"zip1 v16.8h, v18.8h, v17.8h\n"
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"str q16, [%x[out_ptr], #0x0]\n"
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"add %x[out_ptr], %x[out_ptr], #0x10\n"
238
"beq 8f\n"
239
"subs x20, x20, #0x1\n"
240
"zip2 v16.8h, v18.8h, v17.8h\n"
241
"str q16, [%x[out_ptr], #0x0]\n"
242
"add %x[out_ptr], %x[out_ptr], #0x10\n"
243
"beq 8f\n"
244
"zip2 v18.8h, v22.8h, v21.8h\n"
245
"zip2 v17.8h, v20.8h, v19.8h\n"
246
"subs x20, x20, #0x1\n"
247
"zip1 v16.8h, v18.8h, v17.8h\n"
248
"str q16, [%x[out_ptr], #0x0]\n"
249
"add %x[out_ptr], %x[out_ptr], #0x10\n"
250
"beq 8f\n"
251
"subs x20, x20, #0x1\n"
252
"zip2 v16.8h, v18.8h, v17.8h\n"
253
"str q16, [%x[out_ptr], #0x0]\n"
254
"add %x[out_ptr], %x[out_ptr], #0x10\n"
255
"beq 8f\n"
256
"zip2 v22.8h, v30.8h, v26.8h\n"
257
"zip2 v21.8h, v28.8h, v24.8h\n"
258
"subs x20, x20, #0x1\n"
259
"zip2 v20.8h, v29.8h, v25.8h\n"
260
"zip2 v19.8h, v27.8h, v23.8h\n"
261
"zip1 v18.8h, v22.8h, v21.8h\n"
262
"zip1 v17.8h, v20.8h, v19.8h\n"
263
"zip1 v16.8h, v18.8h, v17.8h\n"
264
"str q16, [%x[out_ptr], #0x0]\n"
265
"add %x[out_ptr], %x[out_ptr], #0x10\n"
266
"beq 8f\n"
267
"subs x20, x20, #0x1\n"
268
"zip2 v16.8h, v18.8h, v17.8h\n"
269
"str q16, [%x[out_ptr], #0x0]\n"
270
"add %x[out_ptr], %x[out_ptr], #0x10\n"
271
"beq 8f\n"
272
"zip2 v17.8h, v22.8h, v21.8h\n"
273
"zip2 v16.8h, v20.8h, v19.8h\n"
274
"zip1 v16.8h, v17.8h, v16.8h\n"
275
"str q16, [%x[out_ptr], #0x0]\n"
276
"add %x[out_ptr], %x[out_ptr], #0x10\n"
277
"8:"
// Odds skip
278
: [out_ptr]
"+&r"
(out_ptr), [width]
"+&r"
(width)
279
: [height]
"r"
(height), [in]
"r"
(in), [row_offset]
"r"
(row_offset)
280
:
"cc"
,
"memory"
,
"v16"
,
"v17"
,
"v18"
,
"v19"
,
"v20"
,
"v21"
,
"v22"
,
"v23"
,
"v24"
,
"v25"
,
"v26"
,
"v27"
,
"v28"
,
"v29"
,
"v30"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"x24"
,
"x25"
,
"x26"
,
"x27"
,
"x28"
281
);
282
}
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#endif // __aarch64__
src
core
NEON
kernels
arm_gemm
indirect-interleaves
a64_interleave8_block1_u8_u16.hpp
Generated on Mon Apr 29 2024 10:53:55 for Compute Library by
1.8.17