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a64_interleave8_block4_fp32_bf16.hpp
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/*
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* Copyright (c) 2021, 2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef __aarch64__
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template
<>
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void
interleave_block<8, 4, VLType::None, false>(
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bfloat16
* &out_ptr,
const
float
*
const
* in,
size_t
width,
size_t
height,
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size_t
row_offset,
bool
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)
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{
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__asm__ __volatile__(
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"ldr x28, [%x[in], #0x0]\n"
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"ldr x27, [%x[in], #0x8]\n"
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"cmp %x[height], #0x8\n"
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"add x28, x28, %x[row_offset], LSL #2\n"
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"ldr x26, [%x[in], #0x10]\n"
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"ldr x25, [%x[in], #0x18]\n"
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"add x27, x27, %x[row_offset], LSL #2\n"
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"add x26, x26, %x[row_offset], LSL #2\n"
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"ldr x24, [%x[in], #0x20]\n"
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"ldr x23, [%x[in], #0x28]\n"
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"add x25, x25, %x[row_offset], LSL #2\n"
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"add x24, x24, %x[row_offset], LSL #2\n"
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"ldr x22, [%x[in], #0x30]\n"
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"ldr x21, [%x[in], #0x38]\n"
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"add x23, x23, %x[row_offset], LSL #2\n"
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"add x22, x22, %x[row_offset], LSL #2\n"
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"add x21, x21, %x[row_offset], LSL #2\n"
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"beq 1f\n"
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"cmp %x[height], #0x2\n"
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"csel x27, x27, x28, GE\n"
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"csel x26, x26, x28, GT\n"
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"cmp %x[height], #0x4\n"
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"csel x25, x25, x28, GE\n"
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"csel x24, x24, x28, GT\n"
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"cmp %x[height], #0x6\n"
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"mov x21, x28\n"
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"csel x23, x23, x28, GE\n"
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"csel x22, x22, x28, GT\n"
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"1:"
// no_pointer_adj
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"cmp %x[width], #0x4\n"
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"prfm pldl1keep, [x28, #0x0]\n"
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"prfm pldl1keep, [x27, #0x0]\n"
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"prfm pldl1keep, [x26, #0x0]\n"
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"prfm pldl1keep, [x25, #0x0]\n"
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"prfm pldl1keep, [x24, #0x0]\n"
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"prfm pldl1keep, [x23, #0x0]\n"
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"prfm pldl1keep, [x22, #0x0]\n"
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"prfm pldl1keep, [x21, #0x0]\n"
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"prfm pldl1keep, [x28, #0x40]\n"
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"prfm pldl1keep, [x27, #0x40]\n"
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"prfm pldl1keep, [x26, #0x40]\n"
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"prfm pldl1keep, [x25, #0x40]\n"
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"prfm pldl1keep, [x24, #0x40]\n"
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"prfm pldl1keep, [x23, #0x40]\n"
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"prfm pldl1keep, [x22, #0x40]\n"
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"prfm pldl1keep, [x21, #0x40]\n"
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"blt 3f\n"
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"2:"
// Main loop head
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"ldr q17, [x28], #0x10\n"
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"ldr q16, [x26], #0x10\n"
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".inst 0x0ea16a37 // bfcvtn v23.4h, v17.4s\n"
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".inst 0x0ea16a16 // bfcvtn v22.4h, v16.4s\n"
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"ldr q17, [x24], #0x10\n"
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"ldr q16, [x22], #0x10\n"
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".inst 0x0ea16a35 // bfcvtn v21.4h, v17.4s\n"
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".inst 0x0ea16a14 // bfcvtn v20.4h, v16.4s\n"
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"ldr q19, [x27], #0x10\n"
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"ldr q18, [x25], #0x10\n"
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"subs %x[width], %x[width], #0x4\n"
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"cmp %x[width], #0x4\n"
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"ldr q17, [x23], #0x10\n"
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"ldr q16, [x21], #0x10\n"
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".inst 0x4ea16a77 // bfcvtn2 v23.8h, v19.4s\n"
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".inst 0x4ea16a56 // bfcvtn2 v22.8h, v18.4s\n"
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"prfm pldl1keep, [x28, #0x70]\n"
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"prfm pldl1keep, [x27, #0x70]\n"
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".inst 0x4ea16a35 // bfcvtn2 v21.8h, v17.4s\n"
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".inst 0x4ea16a14 // bfcvtn2 v20.8h, v16.4s\n"
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"prfm pldl1keep, [x26, #0x70]\n"
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"prfm pldl1keep, [x25, #0x70]\n"
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"str q23, [%x[out_ptr], #0x0]\n"
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"prfm pldl1keep, [x24, #0x70]\n"
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"prfm pldl1keep, [x23, #0x70]\n"
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"str q22, [%x[out_ptr], #0x10]\n"
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"prfm pldl1keep, [x22, #0x70]\n"
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"prfm pldl1keep, [x21, #0x70]\n"
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"str q21, [%x[out_ptr], #0x20]\n"
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"str q20, [%x[out_ptr], #0x30]\n"
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"add %x[out_ptr], %x[out_ptr], #0x40\n"
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"bge 2b\n"
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"3:"
// Main loop skip
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"cbz %x[width], 6f\n"
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"tbz %x[width], #1, 4f\n"
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"ldr d19, [x28], #0x8\n"
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"ldr d23, [x27], #0x8\n"
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"mov x20, #0x1\n"
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"ldr d18, [x26], #0x8\n"
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"ldr d22, [x25], #0x8\n"
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"ldr d17, [x24], #0x8\n"
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"ldr d21, [x23], #0x8\n"
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"ldr d16, [x22], #0x8\n"
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"ldr d20, [x21], #0x8\n"
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"tbz %x[width], #0, 5f\n"
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"ld1 { v19.s }[2], [x28]\n"
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"ld1 { v23.s }[2], [x27]\n"
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"ld1 { v18.s }[2], [x26]\n"
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"ld1 { v22.s }[2], [x25]\n"
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"ld1 { v17.s }[2], [x24]\n"
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"ld1 { v21.s }[2], [x23]\n"
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"ld1 { v16.s }[2], [x22]\n"
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"ld1 { v20.s }[2], [x21]\n"
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"b 5f\n"
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"4:"
// odd_loads_1_0
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"ldr s19, [x28, #0x0]\n"
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"ldr s23, [x27, #0x0]\n"
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"mov x20, #0x1\n"
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"ldr s18, [x26, #0x0]\n"
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"ldr s22, [x25, #0x0]\n"
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"ldr s17, [x24, #0x0]\n"
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"ldr s21, [x23, #0x0]\n"
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"ldr s16, [x22, #0x0]\n"
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"ldr s20, [x21, #0x0]\n"
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"5:"
// Odd load end
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".inst 0x0ea16a73 // bfcvtn v19.4h, v19.4s\n"
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".inst 0x0ea16a52 // bfcvtn v18.4h, v18.4s\n"
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".inst 0x0ea16a31 // bfcvtn v17.4h, v17.4s\n"
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".inst 0x0ea16a10 // bfcvtn v16.4h, v16.4s\n"
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".inst 0x4ea16af3 // bfcvtn2 v19.8h, v23.4s\n"
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".inst 0x4ea16ad2 // bfcvtn2 v18.8h, v22.4s\n"
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"str q19, [%x[out_ptr], #0x0]\n"
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".inst 0x4ea16ab1 // bfcvtn2 v17.8h, v21.4s\n"
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".inst 0x4ea16a90 // bfcvtn2 v16.8h, v20.4s\n"
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"str q18, [%x[out_ptr], #0x10]\n"
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"str q17, [%x[out_ptr], #0x20]\n"
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"str q16, [%x[out_ptr], #0x30]\n"
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"add %x[out_ptr], %x[out_ptr], #0x40\n"
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"6:"
// Odds skip
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: [out_ptr]
"+&r"
(out_ptr), [width]
"+&r"
(width)
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: [height]
"r"
(height), [in]
"r"
(in), [row_offset]
"r"
(row_offset)
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:
"cc"
,
"memory"
,
"v16"
,
"v17"
,
"v18"
,
"v19"
,
"v20"
,
"v21"
,
"v22"
,
"v23"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"x24"
,
"x25"
,
"x26"
,
"x27"
,
"x28"
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);
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}
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#endif // __aarch64__
arm_gemm::bfloat16
arm_compute::bfloat16 bfloat16
Definition:
bfloat.hpp:30
src
core
NEON
kernels
arm_gemm
indirect-interleaves
a64_interleave8_block4_fp32_bf16.hpp
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