24.04
generic.cpp
Go to the documentation of this file.
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/*
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* Copyright (c) 2021-2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <cstdint>
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#include <cstddef>
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#if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
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namespace
arm_conv
{
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namespace
pooling
{
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void
a64_fp16_nhwc_max_generic_depthfirst_impl(
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const
uint64_t,
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const
uint64_t n_valid_cells,
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uint64_t n_channels,
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const
__fp16 *
const
*
const
inptrs,
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__fp16 *outptr
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)
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{
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__asm__ __volatile__(
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"cmp %x[n_channels], #0x20\n"
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"mov x27, #0x0\n"
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"mov x26, #0x10\n"
// cntb _, ALL, #1
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"mov x24, #0x20\n"
// cntb _, ALL, #2
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"mov x23, #0x30\n"
// cntb _, ALL, #3
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"blt 7f\n"
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"1:"
// 4-vectors of channels
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"mov w20, #0xfc00\n"
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"lsr x25, %x[n_valid_cells], #0x2\n"
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"dup v8.8h, w20\n"
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"dup v7.8h, w20\n"
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"dup v6.8h, w20\n"
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"dup v5.8h, w20\n"
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"mov x22, %x[inptrs]\n"
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"cbz x25, 4f\n"
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"ldp x21, x20, [x22, #0x0]\n"
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"ldr q4, [x21, x27]\n"
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"subs x25, x25, #0x1\n"
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"ldr q3, [x20, x27]\n"
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"ldr q2, [x21, x26]\n"
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"ldr q1, [x20, x26]\n"
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"ldr q0, [x21, x24]\n"
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"ldr q31, [x20, x24]\n"
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"ldr q30, [x21, x23]\n"
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"ldr q29, [x20, x23]\n"
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"ldp x21, x20, [x22, #0x10]\n"
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"add x22, x22, #0x20\n"
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"ldr q28, [x21, x27]\n"
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"ldr q22, [x20, x27]\n"
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"ldr q27, [x21, x26]\n"
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"ldr q21, [x20, x26]\n"
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"ldr q26, [x21, x24]\n"
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"ldr q20, [x20, x24]\n"
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"ldr q25, [x21, x23]\n"
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"ldr q24, [x20, x23]\n"
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"beq 3f\n"
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"2:"
// 4-vectors of channels: 4 inputs loop
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"fmax v23.8h, v4.8h, v3.8h\n"
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"fmax v19.8h, v28.8h, v22.8h\n"
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"ldp x21, x20, [x22, #0x0]\n"
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"ldr q4, [x21, x27]\n"
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"ldr q3, [x20, x27]\n"
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"fmax v22.8h, v2.8h, v1.8h\n"
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"ldr q2, [x21, x26]\n"
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"fmax v18.8h, v27.8h, v21.8h\n"
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"ldr q1, [x20, x26]\n"
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"fmax v21.8h, v0.8h, v31.8h\n"
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"ldr q0, [x21, x24]\n"
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"fmax v17.8h, v26.8h, v20.8h\n"
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"ldr q31, [x20, x24]\n"
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"fmax v20.8h, v30.8h, v29.8h\n"
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"ldr q30, [x21, x23]\n"
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"fmax v16.8h, v25.8h, v24.8h\n"
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"ldr q29, [x20, x23]\n"
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"fmax v19.8h, v23.8h, v19.8h\n"
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"fmax v18.8h, v22.8h, v18.8h\n"
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"ldp x21, x20, [x22, #0x10]\n"
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"ldr q28, [x21, x27]\n"
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"ldr q22, [x20, x27]\n"
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"fmax v17.8h, v21.8h, v17.8h\n"
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"fmax v16.8h, v20.8h, v16.8h\n"
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"ldr q27, [x21, x26]\n"
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"ldr q21, [x20, x26]\n"
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"subs x25, x25, #0x1\n"
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"fmax v8.8h, v8.8h, v19.8h\n"
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"ldr q26, [x21, x24]\n"
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"ldr q20, [x20, x24]\n"
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"fmax v7.8h, v7.8h, v18.8h\n"
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"fmax v6.8h, v6.8h, v17.8h\n"
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"ldr q25, [x21, x23]\n"
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"ldr q24, [x20, x23]\n"
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"fmax v5.8h, v5.8h, v16.8h\n"
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"add x22, x22, #0x20\n"
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"bgt 2b\n"
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"3:"
// 4-vectors of channels: 4 inputs tail
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"fmax v23.8h, v4.8h, v3.8h\n"
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"fmax v19.8h, v28.8h, v22.8h\n"
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"fmax v22.8h, v2.8h, v1.8h\n"
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"fmax v18.8h, v27.8h, v21.8h\n"
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"fmax v21.8h, v0.8h, v31.8h\n"
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"fmax v17.8h, v26.8h, v20.8h\n"
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"fmax v20.8h, v30.8h, v29.8h\n"
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"fmax v16.8h, v25.8h, v24.8h\n"
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"fmax v19.8h, v23.8h, v19.8h\n"
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"fmax v18.8h, v22.8h, v18.8h\n"
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"fmax v17.8h, v21.8h, v17.8h\n"
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"fmax v16.8h, v20.8h, v16.8h\n"
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"fmax v8.8h, v8.8h, v19.8h\n"
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"fmax v7.8h, v7.8h, v18.8h\n"
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"fmax v6.8h, v6.8h, v17.8h\n"
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"fmax v5.8h, v5.8h, v16.8h\n"
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"4:"
// 4-vectors of channels: After loop
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"ands x21, %x[n_valid_cells], #0x3\n"
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"beq 6f\n"
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"5:"
// 4-vectors of channels: Single input loop
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"ldr x20, [x22], #0x8\n"
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"ldr q16, [x20, x27]\n"
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"subs x21, x21, #0x1\n"
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"fmax v8.8h, v8.8h, v16.8h\n"
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"ldr q17, [x20, x26]\n"
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"ldr q16, [x20, x24]\n"
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"fmax v7.8h, v7.8h, v17.8h\n"
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"fmax v6.8h, v6.8h, v16.8h\n"
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"ldr q16, [x20, x23]\n"
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"fmax v5.8h, v5.8h, v16.8h\n"
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"bgt 5b\n"
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"6:"
// 4-vectors of channels: Single input loop: End
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"sub %x[n_channels], %x[n_channels], #0x20\n"
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"cmp %x[n_channels], #0x20\n"
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"str q8, [%x[outptr], x27]\n"
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"str q7, [%x[outptr], x26]\n"
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"add x27, x27, #0x40\n"
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"add x26, x26, #0x40\n"
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"str q6, [%x[outptr], x24]\n"
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"add x24, x24, #0x40\n"
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"str q5, [%x[outptr], x23]\n"
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"add x23, x23, #0x40\n"
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"bge 1b\n"
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"cbz %x[n_channels], 31f\n"
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"7:"
// Single vector of channels
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"cmp %x[n_channels], #0x8\n"
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"blt 14f\n"
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"8:"
// Single vector of channels: Loop
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"mov w20, #0xfc00\n"
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"lsr x25, %x[n_valid_cells], #0x2\n"
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"dup v8.8h, w20\n"
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"mov x22, %x[inptrs]\n"
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"cbz x25, 11f\n"
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"ldp x21, x20, [x22, #0x0]\n"
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"ldr q4, [x21, x27]\n"
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"subs x25, x25, #0x1\n"
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"ldr q3, [x20, x27]\n"
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"ldp x21, x20, [x22, #0x10]\n"
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"add x22, x22, #0x20\n"
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"ldr q28, [x21, x27]\n"
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"ldr q22, [x20, x27]\n"
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"beq 10f\n"
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"9:"
// Single vector of channels: Loop: 4 inputs loop
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"fmax v17.8h, v4.8h, v3.8h\n"
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"fmax v16.8h, v28.8h, v22.8h\n"
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"ldp x21, x20, [x22, #0x0]\n"
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"ldr q4, [x21, x27]\n"
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"ldr q3, [x20, x27]\n"
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"fmax v16.8h, v17.8h, v16.8h\n"
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"ldp x21, x20, [x22, #0x10]\n"
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"subs x25, x25, #0x1\n"
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"ldr q28, [x21, x27]\n"
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"ldr q22, [x20, x27]\n"
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"fmax v8.8h, v8.8h, v16.8h\n"
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"add x22, x22, #0x20\n"
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"bgt 9b\n"
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"10:"
// Single vector of channels: Loop: 4 inputs tail
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"fmax v17.8h, v4.8h, v3.8h\n"
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"fmax v16.8h, v28.8h, v22.8h\n"
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"fmax v16.8h, v17.8h, v16.8h\n"
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"fmax v8.8h, v8.8h, v16.8h\n"
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"11:"
// Single vector of channels: Loop: After loop
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"ands x21, %x[n_valid_cells], #0x3\n"
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"beq 13f\n"
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"12:"
// Single vector of channels: Loop: Single input loop
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"ldr x20, [x22], #0x8\n"
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"ldr q16, [x20, x27]\n"
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"subs x21, x21, #0x1\n"
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"fmax v8.8h, v8.8h, v16.8h\n"
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"bgt 12b\n"
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"13:"
// Single vector of channels: Loop: Single input loop: End
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"sub %x[n_channels], %x[n_channels], #0x8\n"
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"cmp %x[n_channels], #0x8\n"
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"str q8, [%x[outptr], x27]\n"
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"add x27, x27, #0x10\n"
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"bge 8b\n"
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"cbz %x[n_channels], 31f\n"
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"14:"
// Oddments
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"mov w20, #0xfc00\n"
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"lsr x25, %x[n_valid_cells], #0x2\n"
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"dup v8.8h, w20\n"
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"add %x[outptr], %x[outptr], x27\n"
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"mov x24, %x[inptrs]\n"
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"cbz x25, 20f\n"
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"15:"
// Oddments: 4 inputs loop
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"ldp x23, x22, [x24, #0x0]\n"
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"ldp x21, x20, [x24, #0x10]\n"
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"add x24, x24, #0x20\n"
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"add x23, x23, x27\n"
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"add x22, x22, x27\n"
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"add x21, x21, x27\n"
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"movi v4.16b, #0x0\n"
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"movi v3.16b, #0x0\n"
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"add x20, x20, x27\n"
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"movi v28.16b, #0x0\n"
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"movi v22.16b, #0x0\n"
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"tbz %x[n_channels], #2, 17f\n"
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"ldr d4, [x23], #0x8\n"
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"ldr d3, [x22], #0x8\n"
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"ldr d28, [x21], #0x8\n"
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"ldr d22, [x20], #0x8\n"
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"tbz %x[n_channels], #1, 16f\n"
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"ld1 { v4.s }[2], [x23], #0x4\n"
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"ld1 { v3.s }[2], [x22], #0x4\n"
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"ld1 { v28.s }[2], [x21], #0x4\n"
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"ld1 { v22.s }[2], [x20], #0x4\n"
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"tbz %x[n_channels], #0, 19f\n"
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"ld1 { v4.h }[6], [x23], #0x2\n"
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"ld1 { v3.h }[6], [x22], #0x2\n"
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"ld1 { v28.h }[6], [x21], #0x2\n"
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"ld1 { v22.h }[6], [x20], #0x2\n"
249
"b 19f\n"
250
"16:"
// Oddments: 4 inputs loop: Load: Bit 2: Bit 1: Unset
251
"tbz %x[n_channels], #0, 19f\n"
252
"ld1 { v4.h }[4], [x23], #0x2\n"
253
"ld1 { v3.h }[4], [x22], #0x2\n"
254
"ld1 { v28.h }[4], [x21], #0x2\n"
255
"ld1 { v22.h }[4], [x20], #0x2\n"
256
"b 19f\n"
257
"17:"
// Oddments: 4 inputs loop: Load: Bit 2: Unset
258
"tbz %x[n_channels], #1, 18f\n"
259
"ldr s4, [x23], #0x4\n"
260
"ldr s3, [x22], #0x4\n"
261
"ldr s28, [x21], #0x4\n"
262
"ldr s22, [x20], #0x4\n"
263
"tbz %x[n_channels], #0, 19f\n"
264
"ld1 { v4.h }[2], [x23], #0x2\n"
265
"ld1 { v3.h }[2], [x22], #0x2\n"
266
"ld1 { v28.h }[2], [x21], #0x2\n"
267
"ld1 { v22.h }[2], [x20], #0x2\n"
268
"b 19f\n"
269
"18:"
// Oddments: 4 inputs loop: Load: Bit 2: Unset: Bit 1: Unset
270
"tbz %x[n_channels], #0, 19f\n"
271
"ldr h4, [x23], #0x2\n"
272
"ldr h3, [x22], #0x2\n"
273
"ldr h28, [x21], #0x2\n"
274
"ldr h22, [x20], #0x2\n"
275
"19:"
// Oddments: 4 inputs loop: Load: Bit 2: End
276
"fmax v17.8h, v4.8h, v3.8h\n"
277
"fmax v16.8h, v28.8h, v22.8h\n"
278
"subs x25, x25, #0x1\n"
279
"fmax v16.8h, v17.8h, v16.8h\n"
280
"fmax v8.8h, v8.8h, v16.8h\n"
281
"bgt 15b\n"
282
"20:"
// Oddments: After loop
283
"ands x21, %x[n_valid_cells], #0x3\n"
284
"beq 26f\n"
285
"21:"
// Oddments: Single input loop
286
"ldr x23, [x24], #0x8\n"
287
"add x23, x23, x27\n"
288
"movi v4.16b, #0x0\n"
289
"tbz %x[n_channels], #2, 23f\n"
290
"ldr d4, [x23], #0x8\n"
291
"tbz %x[n_channels], #1, 22f\n"
292
"ld1 { v4.s }[2], [x23], #0x4\n"
293
"tbz %x[n_channels], #0, 25f\n"
294
"ld1 { v4.h }[6], [x23], #0x2\n"
295
"b 25f\n"
296
"22:"
// Oddments: Single input loop: Load: Bit 2: Bit 1: Unset
297
"tbz %x[n_channels], #0, 25f\n"
298
"ld1 { v4.h }[4], [x23], #0x2\n"
299
"b 25f\n"
300
"23:"
// Oddments: Single input loop: Load: Bit 2: Unset
301
"tbz %x[n_channels], #1, 24f\n"
302
"ldr s4, [x23], #0x4\n"
303
"tbz %x[n_channels], #0, 25f\n"
304
"ld1 { v4.h }[2], [x23], #0x2\n"
305
"b 25f\n"
306
"24:"
// Oddments: Single input loop: Load: Bit 2: Unset: Bit 1: Unset
307
"tbz %x[n_channels], #0, 25f\n"
308
"ldr h4, [x23], #0x2\n"
309
"25:"
// Oddments: Single input loop: Load: Bit 2: End
310
"subs x21, x21, #0x1\n"
311
"fmax v8.8h, v8.8h, v4.8h\n"
312
"bgt 21b\n"
313
"26:"
// Oddments: Single input loop: End
314
"tbz %x[n_channels], #2, 28f\n"
315
"st1 { v8.d }[0], [%x[outptr]], #0x8\n"
316
"tbz %x[n_channels], #1, 27f\n"
317
"st1 { v8.s }[2], [%x[outptr]], #0x4\n"
318
"tbz %x[n_channels], #0, 30f\n"
319
"st1 { v8.h }[6], [%x[outptr]], #0x2\n"
320
"b 30f\n"
321
"27:"
// Oddments: Store: Bit 2: Bit 1: Unset
322
"tbz %x[n_channels], #0, 30f\n"
323
"st1 { v8.h }[4], [%x[outptr]], #0x2\n"
324
"b 30f\n"
325
"28:"
// Oddments: Store: Bit 2: Unset
326
"tbz %x[n_channels], #1, 29f\n"
327
"st1 { v8.s }[0], [%x[outptr]], #0x4\n"
328
"tbz %x[n_channels], #0, 30f\n"
329
"st1 { v8.h }[2], [%x[outptr]], #0x2\n"
330
"b 30f\n"
331
"29:"
// Oddments: Store: Bit 2: Unset: Bit 1: Unset
332
"tbz %x[n_channels], #0, 30f\n"
333
"st1 { v8.h }[0], [%x[outptr]], #0x2\n"
334
"30:"
// Oddments: Store: Bit 2: End
335
"31:"
// End
336
: [n_channels]
"+&r"
(n_channels), [outptr]
"+&r"
(outptr)
337
: [inptrs]
"r"
(inptrs), [n_valid_cells]
"r"
(n_valid_cells)
338
:
"cc"
,
"memory"
,
"v0"
,
"v1"
,
"v2"
,
"v3"
,
"v4"
,
"v5"
,
"v6"
,
"v7"
,
"v8"
,
"v16"
,
"v17"
,
"v18"
,
"v19"
,
"v20"
,
"v21"
,
"v22"
,
"v23"
,
"v24"
,
"v25"
,
"v26"
,
"v27"
,
"v28"
,
"v29"
,
"v30"
,
"v31"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"x24"
,
"x25"
,
"x26"
,
"x27"
339
);
340
}
341
342
}
// namespace pooling
343
}
// namespace arm_conv
344
345
#endif // defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
arm_conv::pooling::pooling
template UniquePoolingCommon< float, float > pooling(const PoolingArgs &, const Nothing &)
arm_conv
Definition:
addressing.cpp:30
src
core
NEON
kernels
arm_conv
pooling
kernels
a64_fp16_nhwc_max_generic_depthfirst
generic.cpp
Generated on Mon Apr 29 2024 10:53:54 for Compute Library by
1.8.17