24.04
generic.cpp
Go to the documentation of this file.
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/*
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* Copyright (c) 2022-2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <cstdint>
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#include <cstddef>
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#if defined(ARM_COMPUTE_ENABLE_SME)
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namespace
arm_conv
{
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namespace
pooling
{
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void
sme_fp32_nhwc_avg_generic_depthfirst_impl(
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const
uint64_t window_cells,
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const
uint64_t n_valid_cells,
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uint64_t n_channels,
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const
float
*
const
*
const
inptrs,
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float
*outptr
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)
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{
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const
auto
rescale_value =
static_cast<
float
>
(1.0f /
static_cast<
float
>
(window_cells));
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__asm__ __volatile__(
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".inst 0xd503477f // SMSTART ZA\n"
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"mov x9, #0x0\n"
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"cntw x28\n"
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"cntw x27, ALL, MUL #2\n"
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"cntw x26, ALL, MUL #3\n"
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"ptrue p0.b\n"
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"whilelt p3.s, x9, %x[n_channels]\n"
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"ld1rw { z6.s }, p0/Z, [%x[rescale_ptr]]\n"
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"whilelt p2.s, x28, %x[n_channels]\n"
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"whilelt p1.s, x27, %x[n_channels]\n"
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"whilelt p0.s, x26, %x[n_channels]\n"
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"b.none 7f\n"
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"1:"
// 4-vectors of channels
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"lsr x25, %x[n_valid_cells], #0x2\n"
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"mov z5.b, #0x0\n"
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"mov z4.b, #0x0\n"
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"mov x24, %x[inptrs]\n"
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"mov z3.b, #0x0\n"
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"mov z2.b, #0x0\n"
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"cbz x25, 4f\n"
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"ldp x23, x22, [x24, #0x0]\n"
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"subs x25, x25, #0x1\n"
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"ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n"
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"ldp x21, x20, [x24, #0x10]\n"
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"add x24, x24, #0x20\n"
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"ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n"
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"ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n"
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"ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n"
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"ld1w { z29.s }, p2/Z, [x23, x28, LSL #2]\n"
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"ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n"
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"ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n"
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"ld1w { z18.s }, p2/Z, [x20, x28, LSL #2]\n"
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"ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n"
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"ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n"
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"ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n"
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"ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n"
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"ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n"
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"ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n"
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"ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n"
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"ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n"
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"beq 3f\n"
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"2:"
// 4-vectors of channels: 4 inputs loop
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"fadd z23.s, z1.s, z0.s\n"
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"fadd z19.s, z31.s, z30.s\n"
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"ldp x23, x22, [x24, #0x0]\n"
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"subs x25, x25, #0x1\n"
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"fadd z22.s, z29.s, z22.s\n"
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"fadd z18.s, z28.s, z18.s\n"
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"ldp x21, x20, [x24, #0x10]\n"
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"add x24, x24, #0x20\n"
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"fadd z21.s, z27.s, z21.s\n"
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"fadd z17.s, z26.s, z17.s\n"
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"ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n"
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"fadd z20.s, z25.s, z20.s\n"
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"fadd z16.s, z24.s, z16.s\n"
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"ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n"
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"fadd z19.s, z23.s, z19.s\n"
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"fadd z18.s, z22.s, z18.s\n"
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"ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n"
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"fadd z17.s, z21.s, z17.s\n"
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"fadd z16.s, z20.s, z16.s\n"
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"ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n"
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"fadd z5.s, z5.s, z19.s\n"
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"fadd z4.s, z4.s, z18.s\n"
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"ld1w { z29.s }, p2/Z, [x23, x28, LSL #2]\n"
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"fadd z3.s, z3.s, z17.s\n"
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"fadd z2.s, z2.s, z16.s\n"
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"ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n"
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"ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n"
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"ld1w { z18.s }, p2/Z, [x20, x28, LSL #2]\n"
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"ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n"
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"ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n"
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"ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n"
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"ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n"
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"ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n"
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"ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n"
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"ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n"
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"ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n"
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"bgt 2b\n"
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"3:"
// 4-vectors of channels: 4 inputs tail
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"fadd z23.s, z1.s, z0.s\n"
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"fadd z19.s, z31.s, z30.s\n"
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"fadd z22.s, z29.s, z22.s\n"
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"fadd z18.s, z28.s, z18.s\n"
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"fadd z21.s, z27.s, z21.s\n"
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"fadd z17.s, z26.s, z17.s\n"
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"fadd z20.s, z25.s, z20.s\n"
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"fadd z16.s, z24.s, z16.s\n"
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"fadd z19.s, z23.s, z19.s\n"
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"fadd z18.s, z22.s, z18.s\n"
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"fadd z17.s, z21.s, z17.s\n"
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"fadd z16.s, z20.s, z16.s\n"
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"fadd z5.s, z5.s, z19.s\n"
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"fadd z4.s, z4.s, z18.s\n"
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"fadd z3.s, z3.s, z17.s\n"
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"fadd z2.s, z2.s, z16.s\n"
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"4:"
// 4-vectors of channels: After loop
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"ands x21, %x[n_valid_cells], #0x3\n"
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"beq 6f\n"
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"5:"
// 4-vectors of channels: Single input loop
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"ldr x20, [x24], #0x8\n"
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"ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n"
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"subs x21, x21, #0x1\n"
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"fadd z5.s, z5.s, z16.s\n"
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"ld1w { z16.s }, p2/Z, [x20, x28, LSL #2]\n"
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"fadd z4.s, z4.s, z16.s\n"
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"ld1w { z16.s }, p1/Z, [x20, x27, LSL #2]\n"
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"fadd z3.s, z3.s, z16.s\n"
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"ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n"
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"fadd z2.s, z2.s, z16.s\n"
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"bgt 5b\n"
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"6:"
// 4-vectors of channels: Single input loop: End
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"fmul z5.s, z5.s, z6.s\n"
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"fmul z4.s, z4.s, z6.s\n"
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"st1w { z5.s }, p3, [%x[outptr], x9, LSL #2]\n"
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"incw x9, ALL, MUL #4\n"
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"fmul z3.s, z3.s, z6.s\n"
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"fmul z2.s, z2.s, z6.s\n"
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"st1w { z4.s }, p2, [%x[outptr], x28, LSL #2]\n"
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"incw x28, ALL, MUL #4\n"
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"st1w { z3.s }, p1, [%x[outptr], x27, LSL #2]\n"
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"incw x27, ALL, MUL #4\n"
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"st1w { z2.s }, p0, [%x[outptr], x26, LSL #2]\n"
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"incw x26, ALL, MUL #4\n"
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"whilelt p0.s, x26, %x[n_channels]\n"
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"b.any 1b\n"
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"7:"
// Single vector of channels
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"whilelt p3.s, x9, %x[n_channels]\n"
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"b.none 14f\n"
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"8:"
// Single vector of channels: Loop
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"lsr x25, %x[n_valid_cells], #0x2\n"
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"mov z5.b, #0x0\n"
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"mov x24, %x[inptrs]\n"
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"cbz x25, 11f\n"
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"ldp x20, x22, [x24, #0x0]\n"
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"subs x25, x25, #0x1\n"
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"ld1w { z1.s }, p3/Z, [x20, x9, LSL #2]\n"
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"ldp x21, x20, [x24, #0x10]\n"
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"add x24, x24, #0x20\n"
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"ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n"
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"ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n"
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"ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n"
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"beq 10f\n"
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"9:"
// Single vector of channels: Loop: 4 inputs loop
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"fadd z17.s, z1.s, z0.s\n"
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"fadd z16.s, z31.s, z30.s\n"
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"ldp x23, x22, [x24, #0x0]\n"
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"subs x25, x25, #0x1\n"
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"fadd z16.s, z17.s, z16.s\n"
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"ldp x21, x20, [x24, #0x10]\n"
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"fadd z5.s, z5.s, z16.s\n"
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"add x24, x24, #0x20\n"
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"ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n"
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"ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n"
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"ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n"
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"ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n"
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"bgt 9b\n"
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"10:"
// Single vector of channels: Loop: 4 inputs tail
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"fadd z17.s, z1.s, z0.s\n"
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"fadd z16.s, z31.s, z30.s\n"
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"fadd z16.s, z17.s, z16.s\n"
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"fadd z5.s, z5.s, z16.s\n"
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"11:"
// Single vector of channels: Loop: After loop
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"ands x21, %x[n_valid_cells], #0x3\n"
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"beq 13f\n"
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"12:"
// Single vector of channels: Loop: Single input loop
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"ldr x20, [x24], #0x8\n"
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"ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n"
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"subs x21, x21, #0x1\n"
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"fadd z5.s, z5.s, z16.s\n"
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"bgt 12b\n"
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"13:"
// Single vector of channels: Loop: Single input loop: End
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"fmul z5.s, z5.s, z6.s\n"
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"st1w { z5.s }, p3, [%x[outptr], x9, LSL #2]\n"
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"incw x9\n"
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"whilelt p3.s, x9, %x[n_channels]\n"
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"b.any 8b\n"
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"14:"
// End
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".inst 0xd503467f // SMSTOP\n"
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:
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: [inptrs]
"r"
(inptrs), [n_channels]
"r"
(n_channels), [n_valid_cells]
"r"
(n_valid_cells), [outptr]
"r"
(outptr), [rescale_ptr]
"r"
(&rescale_value)
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:
"cc"
,
"memory"
,
"p0"
,
"p1"
,
"p2"
,
"p3"
,
"p4"
,
"p5"
,
"p6"
,
"p7"
,
"p8"
,
"p9"
,
"p10"
,
"p11"
,
"p12"
,
"p13"
,
"p14"
,
"p15"
,
"x9"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"x24"
,
"x25"
,
"x26"
,
"x27"
,
"x28"
,
"z0"
,
"z1"
,
"z2"
,
"z3"
,
"z4"
,
"z5"
,
"z6"
,
"z7"
,
"z8"
,
"z9"
,
"z10"
,
"z11"
,
"z12"
,
"z13"
,
"z14"
,
"z15"
,
"z16"
,
"z17"
,
"z18"
,
"z19"
,
"z20"
,
"z21"
,
"z22"
,
"z23"
,
"z24"
,
"z25"
,
"z26"
,
"z27"
,
"z28"
,
"z29"
,
"z30"
,
"z31"
227
);
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}
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}
// namespace pooling
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}
// namespace arm_conv
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#endif // defined(ARM_COMPUTE_ENABLE_SME)
arm_conv::pooling::pooling
template UniquePoolingCommon< float, float > pooling(const PoolingArgs &, const Nothing &)
arm_conv
Definition:
addressing.cpp:30
src
core
NEON
kernels
arm_conv
pooling
kernels
sme_fp32_nhwc_avg_generic_depthfirst
generic.cpp
Generated on Mon Apr 29 2024 10:53:54 for Compute Library by
1.8.17