29 #if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS)
34 void sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(
35 const unsigned int n_channels,
36 const __fp16 *
const *
const inptrs,
37 __fp16 *
const *
const outptrs,
38 const bool exclude_padding,
39 const unsigned int pad_left,
40 const unsigned int pad_top,
41 const unsigned int pad_right,
42 const unsigned int pad_bottom
47 const uint64_t n_channels;
48 const __fp16 *
const *
const inptrs;
49 __fp16 *
const *
const outptrs;
50 __fp16 rescale_vals[4];
53 unsigned int channels,
54 const __fp16 *
const *input_ptrs,
55 __fp16 *
const * output_ptrs,
56 bool exclude_padding,
unsigned int pad_left,
unsigned int pad_top,
unsigned int pad_right,
unsigned int pad_bottom
57 ) : n_channels(channels),
61 for (
unsigned int i = 0; i < 2; i++)
63 const int start_i = 1*i -
static_cast<int>(pad_top);
64 const int end_i = std::min<int>(start_i + 3, 4 - pad_top - pad_bottom);
65 const int valid_rows = end_i - std::max<int>(0, start_i);
67 for (
unsigned int j = 0; j < 2; j++)
69 const int start_j = 1*j -
static_cast<int>(pad_left);
70 const int end_j = std::min<int>(start_j + 3, 4 - pad_left - pad_right);
71 const int valid_cols = end_j - std::max<int>(0, start_j);
73 rescale_vals[i*2 + j] =
static_cast<__fp16
>(1.0f /
static_cast<float>(
74 exclude_padding ? valid_rows * valid_cols : 9
81 const KernelArgs
args(n_channels, inptrs, outptrs, exclude_padding,
82 pad_left, pad_top, pad_right, pad_bottom);
85 "ldr x2, [%x[args], %[offsetof_n_channels]]\n"
86 "ldr x21, [%x[args], %[offsetof_outptrs]]\n"
89 "ldr x4, [%x[args], %[offsetof_inptrs]]\n"
90 "ldp x5, x6, [x21, #0x0]\n"
91 "whilelt p2.h, XZR, x20\n"
92 "whilelt p0.h, x3, x2\n"
93 "ldp x7, x8, [x21, #0x10]\n"
94 "ldp x17, x16, [x4, #0x0]\n"
95 "add x15, %x[args], %[offsetof_rescale]\n"
97 "ldp x13, x12, [x4, #0x10]\n"
98 "ldp x11, x10, [x4, #0x20]\n"
99 "ldp x9, x28, [x4, #0x30]\n"
100 "ldp x27, x26, [x4, #0x40]\n"
101 "ldp x25, x24, [x4, #0x50]\n"
102 "ldp x23, x22, [x4, #0x60]\n"
103 "ldp x21, x20, [x4, #0x70]\n"
104 "ld1h { z7.h }, p0/Z, [x10, x3, LSL #1]\n"
105 "ld1h { z6.h }, p0/Z, [x9, x3, LSL #1]\n"
106 "ld1h { z5.h }, p0/Z, [x26, x3, LSL #1]\n"
107 "ld1h { z4.h }, p0/Z, [x25, x3, LSL #1]\n"
108 "ld1h { z3.h }, p0/Z, [x16, x3, LSL #1]\n"
109 "ld1h { z2.h }, p0/Z, [x13, x3, LSL #1]\n"
110 "ld1h { z1.h }, p0/Z, [x11, x3, LSL #1]\n"
111 "ld1h { z31.h }, p0/Z, [x27, x3, LSL #1]\n"
112 "ld1h { z30.h }, p0/Z, [x28, x3, LSL #1]\n"
113 "ld1h { z29.h }, p0/Z, [x24, x3, LSL #1]\n"
114 "ld1h { z28.h }, p0/Z, [x22, x3, LSL #1]\n"
115 "ld1h { z27.h }, p0/Z, [x21, x3, LSL #1]\n"
116 "ld1h { z26.h }, p0/Z, [x17, x3, LSL #1]\n"
117 "ld1h { z25.h }, p0/Z, [x12, x3, LSL #1]\n"
118 "ld1h { z24.h }, p0/Z, [x23, x3, LSL #1]\n"
119 "ld1h { z23.h }, p0/Z, [x20, x3, LSL #1]\n"
121 "whilelt p1.h, x3, x2\n"
122 "ld1rqh { z0.h }, p2/Z, [x15]\n"
125 "fadd z17.h, z7.h, z6.h\n"
126 "fadd z16.h, z5.h, z4.h\n"
127 "ld1h { z7.h }, p1/Z, [x10, x3, LSL #1]\n"
128 "ld1h { z6.h }, p1/Z, [x9, x3, LSL #1]\n"
129 "fadd z19.h, z17.h, z16.h\n"
130 "fadd z18.h, z3.h, z2.h\n"
131 "ld1h { z5.h }, p1/Z, [x26, x3, LSL #1]\n"
132 "ld1h { z4.h }, p1/Z, [x25, x3, LSL #1]\n"
133 "fadd z17.h, z1.h, z31.h\n"
134 "fadd z22.h, z30.h, z29.h\n"
135 "ld1h { z3.h }, p1/Z, [x16, x3, LSL #1]\n"
136 "ld1h { z2.h }, p1/Z, [x13, x3, LSL #1]\n"
137 "fadd z16.h, z28.h, z27.h\n"
138 "fadd z21.h, z18.h, z19.h\n"
139 "ld1h { z1.h }, p1/Z, [x11, x3, LSL #1]\n"
140 "ld1h { z31.h }, p1/Z, [x27, x3, LSL #1]\n"
141 "fadd z20.h, z16.h, z19.h\n"
142 "fadd z19.h, z26.h, z17.h\n"
143 "ld1h { z30.h }, p1/Z, [x28, x3, LSL #1]\n"
144 "ld1h { z29.h }, p1/Z, [x24, x3, LSL #1]\n"
145 "fadd z18.h, z25.h, z22.h\n"
146 "fadd z17.h, z24.h, z17.h\n"
147 "ld1h { z28.h }, p1/Z, [x22, x3, LSL #1]\n"
148 "ld1h { z27.h }, p1/Z, [x21, x3, LSL #1]\n"
149 "fadd z16.h, z23.h, z22.h\n"
150 "ld1h { z26.h }, p1/Z, [x17, x3, LSL #1]\n"
151 "ld1h { z25.h }, p1/Z, [x12, x3, LSL #1]\n"
152 "fadd z19.h, z21.h, z19.h\n"
153 "ld1h { z24.h }, p1/Z, [x23, x3, LSL #1]\n"
154 "ld1h { z23.h }, p1/Z, [x20, x3, LSL #1]\n"
156 "fadd z18.h, z21.h, z18.h\n"
157 "fadd z17.h, z17.h, z20.h\n"
158 "fadd z16.h, z16.h, z20.h\n"
159 "whilelt p0.h, x14, x2\n"
160 "whilelt p1.h, x3, x2\n"
161 "fmul z19.h, z19.h, z0.h[0]\n"
162 "fmul z18.h, z18.h, z0.h[1]\n"
163 "st1h { z19.h }, p0, [x5, x14, LSL #1]\n"
164 "fmul z17.h, z17.h, z0.h[2]\n"
165 "fmul z16.h, z16.h, z0.h[3]\n"
166 "st1h { z18.h }, p0, [x6, x14, LSL #1]\n"
167 "st1h { z17.h }, p0, [x7, x14, LSL #1]\n"
168 "st1h { z16.h }, p0, [x8, x14, LSL #1]\n"
172 "fadd z17.h, z7.h, z6.h\n"
173 "fadd z16.h, z5.h, z4.h\n"
174 "whilelt p0.h, x14, x2\n"
175 "fadd z20.h, z17.h, z16.h\n"
176 "fadd z18.h, z3.h, z2.h\n"
177 "fadd z17.h, z1.h, z31.h\n"
178 "fadd z19.h, z30.h, z29.h\n"
179 "fadd z16.h, z28.h, z27.h\n"
180 "fadd z21.h, z18.h, z20.h\n"
181 "fadd z20.h, z16.h, z20.h\n"
182 "fadd z16.h, z26.h, z17.h\n"
183 "fadd z18.h, z25.h, z19.h\n"
184 "fadd z17.h, z24.h, z17.h\n"
185 "fadd z19.h, z23.h, z19.h\n"
186 "fadd z16.h, z21.h, z16.h\n"
187 "fmul z16.h, z16.h, z0.h[0]\n"
188 "st1h { z16.h }, p0, [x5, x14, LSL #1]\n"
189 "fadd z18.h, z21.h, z18.h\n"
190 "fadd z17.h, z17.h, z20.h\n"
191 "fmul z18.h, z18.h, z0.h[1]\n"
192 "fmul z17.h, z17.h, z0.h[2]\n"
193 "fadd z16.h, z19.h, z20.h\n"
194 "fmul z16.h, z16.h, z0.h[3]\n"
195 "st1h { z18.h }, p0, [x6, x14, LSL #1]\n"
196 "st1h { z17.h }, p0, [x7, x14, LSL #1]\n"
197 "st1h { z16.h }, p0, [x8, x14, LSL #1]\n"
199 : [
args]
"r" (&
args), [offsetof_inptrs]
"I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels]
"I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs]
"I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale]
"I" (offsetof(KernelArgs, rescale_vals))
200 :
"cc",
"memory",
"p0",
"p1",
"p2",
"x2",
"x3",
"x4",
"x5",
"x6",
"x7",
"x8",
"x9",
"x10",
"x11",
"x12",
"x13",
"x14",
"x15",
"x16",
"x17",
"x20",
"x21",
"x22",
"x23",
"x24",
"x25",
"x26",
"x27",
"x28",
"z0",
"z1",
"z2",
"z3",
"z4",
"z5",
"z6",
"z7",
"z16",
"z17",
"z18",
"z19",
"z20",
"z21",
"z22",
"z23",
"z24",
"z25",
"z26",
"z27",
"z28",
"z29",
"z30",
"z31"
207 #endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS)