24.04
generic.cpp
Go to the documentation of this file.
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/*
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* Copyright (c) 2017-2018 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef __arm__
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#include <arm_neon.h>
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#include "../../asmlib.hpp"
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// Kernel implementation.
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//
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// Assume that "Apanel" points to a chunk of A blocks (each size 6xK) in read-order.
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// Assume that "Bpanel" points to a chunk of B blocks (each size 8xK) in read-order.
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// Assume that "Cpanel" points to a chunk of C output blocks (each size
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// 8x6), the chunks being arranged in a row major fashion.
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//
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// Note that the intent of this is that either ablocks or bblocks will be 1
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// - this construction allows the output loop to proceed in either order.
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namespace
arm_gemm
{
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void
a32_sgemm_8x6(
const
float
*Apanel,
const
float
*Bpanel,
float
*Cpanel,
int
ablocks,
int
bblocks,
int
K
) {
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const
float
*a_ptr = Apanel;
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float
*c_ptr = Cpanel;
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for
(
int
yb=0; yb<ablocks; yb++) {
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const
float
*a_ptr0 = a_ptr;
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const
float
*b_ptr = Bpanel;
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for
(
int
xb=0; xb<bblocks; xb++) {
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a_ptr = a_ptr0;
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int
tails = (
K
& 3);
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if
(tails == 0) {
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tails = 4;
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}
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int
k = ((
K
+3)/4) - 1;
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__asm __volatile (
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"vmov.i32 q4, #0\n"
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"vld1.32 {d0-d1}, [%[a_ptr] :64]!\n"
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"vmov.i32 q5, #0\n"
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"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
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"vmov.i32 q6, #0\n"
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ASM_PREFETCH
(
"[%[a_ptr], #48]"
)
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"vmov.i32 q7, #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #48]"
)
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"vmov.i32 q8, #0\n"
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ASM_PREFETCH
(
"[%[a_ptr], #112]"
)
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"vmov.i32 q9, #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #112]"
)
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"vmov.i32 q10, #0\n"
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"vmov.i32 q11, #0\n"
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"vmov.i32 q12, #0\n"
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"vmov.i32 q13, #0\n"
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ASM_PREFETCH
(
"[%[a_ptr], #176]"
)
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"vmov.i32 q14, #0\n"
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ASM_PREFETCH
(
"[%[b_ptr], #176]"
)
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"vmov.i32 q15, #0\n"
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"cmp %[k], #0\n"
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"beq 6f\n"
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"1:\n"
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// Unroll 0
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"vmla.f32 q4, q2, d0[0]\n"
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"vld1.32 {d2-d3}, [%[a_ptr] :64]!\n"
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"vmla.f32 q5, q2, d0[1]\n"
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"vmla.f32 q6, q2, d1[0]\n"
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"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
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"vmla.f32 q7, q2, d1[1]\n"
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"vmla.f32 q8, q2, d2[0]\n"
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"vmla.f32 q9, q2, d2[1]\n"
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"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
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"vmla.f32 q10, q3, d0[0]\n"
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"vmla.f32 q11, q3, d0[1]\n"
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"vmla.f32 q12, q3, d1[0]\n"
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"vmla.f32 q13, q3, d1[1]\n"
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"vld1.32 {d0-d1}, [%[a_ptr] :64]!\n"
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"vmla.f32 q14, q3, d2[0]\n"
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"vmla.f32 q15, q3, d2[1]\n"
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"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
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// Unroll 1
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"vmla.f32 q4, q2, d3[0]\n"
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"subs %[k], %[k], #1\n"
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"vmla.f32 q5, q2, d3[1]\n"
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ASM_PREFETCH
(
"[%[a_ptr], #208]"
)
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"vmla.f32 q6, q2, d0[0]\n"
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"vmla.f32 q7, q2, d0[1]\n"
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ASM_PREFETCH
(
"[%[b_ptr], #192]"
)
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"vmla.f32 q8, q2, d1[0]\n"
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"vmla.f32 q9, q2, d1[1]\n"
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"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
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"vmla.f32 q10, q3, d3[0]\n"
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"vmla.f32 q11, q3, d3[1]\n"
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"vld1.32 {d2-d3}, [%[a_ptr] :64]!\n"
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"vmla.f32 q12, q3, d0[0]\n"
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"vmla.f32 q13, q3, d0[1]\n"
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"vmla.f32 q14, q3, d1[0]\n"
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"vmla.f32 q15, q3, d1[1]\n"
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"vld1.32 {d0-d1}, [%[a_ptr] :64]!\n"
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// Unroll 2
126
"vmla.f32 q4, q2, d2[0]\n"
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"vmla.f32 q5, q2, d2[1]\n"
128
"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
129
"vmla.f32 q6, q2, d3[0]\n"
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"vmla.f32 q7, q2, d3[1]\n"
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ASM_PREFETCH
(
"[%[a_ptr], #240]"
)
132
"vmla.f32 q8, q2, d0[0]\n"
133
"vmla.f32 q9, q2, d0[1]\n"
134
"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
135
136
"vmla.f32 q10, q3, d2[0]\n"
137
"vmla.f32 q11, q3, d2[1]\n"
138
ASM_PREFETCH
(
"[%[b_ptr], #208]"
)
139
"vmla.f32 q12, q3, d3[0]\n"
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"vmla.f32 q13, q3, d3[1]\n"
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"vld1.32 {d2-d3}, [%[a_ptr] :64]!\n"
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"vmla.f32 q14, q3, d0[0]\n"
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"vmla.f32 q15, q3, d0[1]\n"
144
"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
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146
// Unroll 3
147
"vmla.f32 q4, q2, d1[0]\n"
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"vmla.f32 q5, q2, d1[1]\n"
149
"vmla.f32 q6, q2, d2[0]\n"
150
"vmla.f32 q7, q2, d2[1]\n"
151
"vmla.f32 q8, q2, d3[0]\n"
152
"vmla.f32 q9, q2, d3[1]\n"
153
"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
154
155
"vmla.f32 q10, q3, d1[0]\n"
156
"vmla.f32 q11, q3, d1[1]\n"
157
"vld1.32 {d0-d1}, [%[a_ptr] :64]!\n"
158
"vmla.f32 q12, q3, d2[0]\n"
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"vmla.f32 q13, q3, d2[1]\n"
160
"vmla.f32 q14, q3, d3[0]\n"
161
"vmla.f32 q15, q3, d3[1]\n"
162
"bne 1b\n"
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164
// Branch here if we never execute main loop.
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"6:\n"
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// "Tails" shows how many multiply blocks are needed at the
168
// end, must be 1-4 inclusive. Bail out to alternative tail
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// immediately if it's 1.
170
"subs %[tails], %[tails], #1\n"
171
"beq 3f\n"
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173
// Detached final iteration
174
// Unroll 0
175
"vmla.f32 q4, q2, d0[0]\n"
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"vld1.32 {d2-d3}, [%[a_ptr] :64]!\n"
177
"vmla.f32 q5, q2, d0[1]\n"
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"vmla.f32 q6, q2, d1[0]\n"
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"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
180
"vmla.f32 q7, q2, d1[1]\n"
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"vmla.f32 q8, q2, d2[0]\n"
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"subs %[tails], %[tails], #1\n"
183
"vmla.f32 q9, q2, d2[1]\n"
184
"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
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186
"vmla.f32 q10, q3, d0[0]\n"
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"vmla.f32 q11, q3, d0[1]\n"
188
"vmla.f32 q12, q3, d1[0]\n"
189
"vmla.f32 q13, q3, d1[1]\n"
190
"vld1.32 {d0-d1}, [%[a_ptr] :64]!\n"
191
"vmla.f32 q14, q3, d2[0]\n"
192
"vmla.f32 q15, q3, d2[1]\n"
193
"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
194
"beq 4f\n"
195
196
// Unroll 1
197
"vmla.f32 q4, q2, d3[0]\n"
198
"vmla.f32 q5, q2, d3[1]\n"
199
"subs %[tails], %[tails], #1\n"
200
"vmla.f32 q6, q2, d0[0]\n"
201
"vmla.f32 q7, q2, d0[1]\n"
202
"vmla.f32 q8, q2, d1[0]\n"
203
"vmla.f32 q9, q2, d1[1]\n"
204
"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
205
206
"vmla.f32 q10, q3, d3[0]\n"
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"vmla.f32 q11, q3, d3[1]\n"
208
"vld1.32 {d2-d3}, [%[a_ptr] :64]!\n"
209
"vmla.f32 q12, q3, d0[0]\n"
210
"vmla.f32 q13, q3, d0[1]\n"
211
"vmla.f32 q14, q3, d1[0]\n"
212
"vmla.f32 q15, q3, d1[1]\n"
213
"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
214
"beq 5f\n"
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// Unroll 2
217
"vld1.32 {d0-d1}, [%[a_ptr] :64]!\n"
218
"vmla.f32 q4, q2, d2[0]\n"
219
"vmla.f32 q5, q2, d2[1]\n"
220
"vmla.f32 q6, q2, d3[0]\n"
221
"vmla.f32 q7, q2, d3[1]\n"
222
"vmla.f32 q8, q2, d0[0]\n"
223
"vmla.f32 q9, q2, d0[1]\n"
224
"vld1.32 {d4-d5}, [%[b_ptr] :128]!\n"
225
226
"vmla.f32 q10, q3, d2[0]\n"
227
"vmla.f32 q11, q3, d2[1]\n"
228
"vmla.f32 q12, q3, d3[0]\n"
229
"vmla.f32 q13, q3, d3[1]\n"
230
"vld1.32 {d2-d3}, [%[a_ptr] :64]!\n"
231
"vmla.f32 q14, q3, d0[0]\n"
232
"vmla.f32 q15, q3, d0[1]\n"
233
"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
234
235
// Unroll 3
236
"vmla.f32 q4, q2, d1[0]\n"
237
"vmla.f32 q10, q3, d1[0]\n"
238
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
239
"vmla.f32 q5, q2, d1[1]\n"
240
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
241
"vmla.f32 q11, q3, d1[1]\n"
242
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
243
"vmla.f32 q6, q2, d2[0]\n"
244
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
245
"vmla.f32 q12, q3, d2[0]\n"
246
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
247
"vmla.f32 q7, q2, d2[1]\n"
248
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
249
"vmla.f32 q13, q3, d2[1]\n"
250
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
251
"vmla.f32 q8, q2, d3[0]\n"
252
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
253
"vmla.f32 q14, q3, d3[0]\n"
254
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
255
"vmla.f32 q9, q2, d3[1]\n"
256
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
257
"vmla.f32 q15, q3, d3[1]\n"
258
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
259
"b 2f\n"
260
261
// tails==1 final tail
262
"3:\n"
263
"vmla.f32 q4, q2, d0[0]\n"
264
"vld1.32 {d2}, [%[a_ptr] :64]!\n"
265
"vmla.f32 q5, q2, d0[1]\n"
266
"vld1.32 {d6-d7}, [%[b_ptr] :128]!\n"
267
"vmla.f32 q6, q2, d1[0]\n"
268
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
269
"vmla.f32 q10, q3, d0[0]\n"
270
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
271
"vmla.f32 q11, q3, d0[1]\n"
272
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
273
"vmla.f32 q12, q3, d1[0]\n"
274
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
275
"vmla.f32 q7, q2, d1[1]\n"
276
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
277
"vmla.f32 q13, q3, d1[1]\n"
278
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
279
"vmla.f32 q8, q2, d2[0]\n"
280
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
281
"vmla.f32 q14, q3, d2[0]\n"
282
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
283
"vmla.f32 q9, q2, d2[1]\n"
284
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
285
"vmla.f32 q15, q3, d2[1]\n"
286
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
287
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
288
"b 2f\n"
289
290
// tails==2 final tail
291
"4:\n"
292
"vmla.f32 q4, q2, d3[0]\n"
293
"vmla.f32 q10, q3, d3[0]\n"
294
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
295
"vmla.f32 q5, q2, d3[1]\n"
296
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
297
"vmla.f32 q11, q3, d3[1]\n"
298
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
299
"vmla.f32 q6, q2, d0[0]\n"
300
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
301
"vmla.f32 q12, q3, d0[0]\n"
302
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
303
"vmla.f32 q7, q2, d0[1]\n"
304
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
305
"vmla.f32 q13, q3, d0[1]\n"
306
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
307
"vmla.f32 q8, q2, d1[0]\n"
308
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
309
"vmla.f32 q14, q3, d1[0]\n"
310
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
311
"vmla.f32 q9, q2, d1[1]\n"
312
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
313
"vmla.f32 q15, q3, d1[1]\n"
314
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
315
"b 2f\n"
316
317
// tails==3 final tail
318
"5:\n"
319
"vmla.f32 q4, q2, d2[0]\n"
320
"vld1.32 {d0}, [%[a_ptr] :64]!\n"
321
"vmla.f32 q5, q2, d2[1]\n"
322
"vmla.f32 q6, q2, d3[0]\n"
323
"vst1.32 {d8-d9}, [%[c_ptr] :128]!\n"
324
"vmla.f32 q10, q3, d2[0]\n"
325
"vst1.32 {d20-d21}, [%[c_ptr] :128]!\n"
326
"vmla.f32 q11, q3, d2[1]\n"
327
"vst1.32 {d10-d11}, [%[c_ptr] :128]!\n"
328
"vmla.f32 q12, q3, d3[0]\n"
329
"vst1.32 {d22-d23}, [%[c_ptr] :128]!\n"
330
"vmla.f32 q7, q2, d3[1]\n"
331
"vst1.32 {d12-d13}, [%[c_ptr] :128]!\n"
332
"vmla.f32 q13, q3, d3[1]\n"
333
"vst1.32 {d24-d25}, [%[c_ptr] :128]!\n"
334
"vmla.f32 q8, q2, d0[0]\n"
335
"vst1.32 {d14-d15}, [%[c_ptr] :128]!\n"
336
"vmla.f32 q14, q3, d0[0]\n"
337
"vst1.32 {d26-d27}, [%[c_ptr] :128]!\n"
338
"vmla.f32 q9, q2, d0[1]\n"
339
"vst1.32 {d16-d17}, [%[c_ptr] :128]!\n"
340
"vmla.f32 q15, q3, d0[1]\n"
341
"vst1.32 {d28-d29}, [%[c_ptr] :128]!\n"
342
"vst1.32 {d18-d19}, [%[c_ptr] :128]!\n"
343
344
"2:\n"
345
"vst1.32 {d30-d31}, [%[c_ptr] :128]!\n"
346
: [a_ptr]
"+r"
(a_ptr), [b_ptr]
"+r"
(b_ptr), [c_ptr]
"+r"
(c_ptr), [k]
"+r"
(k), [tails]
"+r"
(tails)
347
:
348
:
"q0"
,
"q1"
,
"q2"
,
"q3"
,
"q4"
,
"q5"
,
"q6"
,
"q7"
,
"q8"
,
"q9"
,
"q10"
,
"q11"
,
"q12"
,
"q13"
,
"q14"
,
"q15"
,
349
"cc"
,
"memory"
350
);
351
}
352
}
353
}
354
355
}
// namespace arm_gemm
356
357
#endif
ASM_PREFETCH
#define ASM_PREFETCH(address)
Definition:
asmlib.hpp:45
arm_gemm
Definition:
barrier.hpp:30
K
unsigned int K
Definition:
CpuGemmAssemblyDispatch.cpp:106
src
core
NEON
kernels
arm_gemm
kernels
a32_sgemm_8x6
generic.cpp
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