24.04
generic.cpp
Go to the documentation of this file.
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/*
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* Copyright (c) 2019-2021, 2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef ARM_COMPUTE_ENABLE_SVE
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#include <cstddef>
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#include "../../bfloat.hpp"
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namespace
arm_gemm
{
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void
sve_interleaved_bf16fp32_mmla_8x3VL(
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const
bfloat16
*Apanel,
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const
bfloat16
*Bpanel,
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float
*Cpanel,
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int
ablocks,
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int
bblocks,
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int
K
) {
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struct
KernelArgs {
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size_t
K
= {};
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const
bfloat16
*Bpanel = {};
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size_t
bblocks = {};
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} ka;
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ka.K = (
K
/4) - 1;
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ka.Bpanel = Bpanel;
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ka.bblocks = bblocks;
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__asm__ __volatile__(
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"ptrue p0.b\n"
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"1:"
// Height loop
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"ldr x23, [%x[args_ptr], %[offsetof_bblocks]]\n"
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"ldr x22, [%x[args_ptr], %[offsetof_Bpanel]]\n"
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"mov x21, %x[Apanel]\n"
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"2:"
// Width loop
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"ldr x20, [%x[args_ptr], %[offsetof_K]]\n"
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"mov %x[Apanel], x21\n"
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"cmp x20, #0x2\n"
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"mov z8.b, #0x0\n"
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"mov z9.b, #0x0\n"
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"ld1h { z4.h }, p0/Z, [x22]\n"
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"mov z10.b, #0x0\n"
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"mov z11.b, #0x0\n"
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"ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n"
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"mov z12.b, #0x0\n"
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"mov z13.b, #0x0\n"
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"ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n"
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"mov z14.b, #0x0\n"
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"mov z15.b, #0x0\n"
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"ld1h { z5.h }, p0/Z, [x22, #1, MUL VL]\n"
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"mov z16.b, #0x0\n"
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"mov z17.b, #0x0\n"
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"ld1rqh { z2.h }, p0/Z, [%x[Apanel], #32]\n"
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"mov z18.b, #0x0\n"
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"mov z19.b, #0x0\n"
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"addvl x22, x22, #2\n"
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"mov z20.b, #0x0\n"
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"mov z21.b, #0x0\n"
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"add %x[Apanel], %x[Apanel], #0x30\n"
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"mov z22.b, #0x0\n"
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"mov z23.b, #0x0\n"
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"mov z24.b, #0x0\n"
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"mov z25.b, #0x0\n"
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"mov z26.b, #0x0\n"
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"mov z27.b, #0x0\n"
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"mov z28.b, #0x0\n"
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"mov z29.b, #0x0\n"
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"mov z30.b, #0x0\n"
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"mov z31.b, #0x0\n"
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"blt 4f\n"
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"3:"
// main loop head
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"ld1rqh { z6.h }, p0/Z, [%x[Apanel]]\n"
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".inst 0x6464e408 // bfmmla z8.s, z0.h, z4.h\n"
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".inst 0x6465e40b // bfmmla z11.s, z0.h, z5.h\n"
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".inst 0x6464e42e // bfmmla z14.s, z1.h, z4.h\n"
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".inst 0x6465e431 // bfmmla z17.s, z1.h, z5.h\n"
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"ld1h { z7.h }, p0/Z, [x22]\n"
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".inst 0x6464e454 // bfmmla z20.s, z2.h, z4.h\n"
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".inst 0x6465e457 // bfmmla z23.s, z2.h, z5.h\n"
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"ld1h { z3.h }, p0/Z, [x22, #1, MUL VL]\n"
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".inst 0x6464e4da // bfmmla z26.s, z6.h, z4.h\n"
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".inst 0x6465e4dd // bfmmla z29.s, z6.h, z5.h\n"
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"ld1h { z5.h }, p0/Z, [x22, #2, MUL VL]\n"
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"ld1h { z4.h }, p0/Z, [x22, #3, MUL VL]\n"
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".inst 0x6467e409 // bfmmla z9.s, z0.h, z7.h\n"
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".inst 0x6463e40c // bfmmla z12.s, z0.h, z3.h\n"
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".inst 0x6467e42f // bfmmla z15.s, z1.h, z7.h\n"
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".inst 0x6463e432 // bfmmla z18.s, z1.h, z3.h\n"
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"sub x20, x20, #0x2\n"
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".inst 0x6467e455 // bfmmla z21.s, z2.h, z7.h\n"
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".inst 0x6463e458 // bfmmla z24.s, z2.h, z3.h\n"
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"cmp x20, #0x2\n"
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".inst 0x6467e4db // bfmmla z27.s, z6.h, z7.h\n"
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".inst 0x6463e4de // bfmmla z30.s, z6.h, z3.h\n"
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"ld1h { z3.h }, p0/Z, [x22, #4, MUL VL]\n"
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".inst 0x6465e40a // bfmmla z10.s, z0.h, z5.h\n"
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".inst 0x6464e40d // bfmmla z13.s, z0.h, z4.h\n"
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"ld1rqh { z0.h }, p0/Z, [%x[Apanel], #16]\n"
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".inst 0x6465e430 // bfmmla z16.s, z1.h, z5.h\n"
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".inst 0x6464e433 // bfmmla z19.s, z1.h, z4.h\n"
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"ld1rqh { z1.h }, p0/Z, [%x[Apanel], #32]\n"
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".inst 0x6465e456 // bfmmla z22.s, z2.h, z5.h\n"
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".inst 0x6464e459 // bfmmla z25.s, z2.h, z4.h\n"
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"ld1h { z7.h }, p0/Z, [x22, #5, MUL VL]\n"
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".inst 0x6465e4dc // bfmmla z28.s, z6.h, z5.h\n"
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".inst 0x6464e4df // bfmmla z31.s, z6.h, z4.h\n"
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"ld1rqh { z5.h }, p0/Z, [%x[Apanel], #48]\n"
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"ld1rqh { z6.h }, p0/Z, [%x[Apanel], #64]\n"
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"ld1h { z2.h }, p0/Z, [x22, #6, MUL VL]\n"
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".inst 0x6463e408 // bfmmla z8.s, z0.h, z3.h\n"
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"ld1h { z4.h }, p0/Z, [x22, #7, MUL VL]\n"
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"addvl x22, x22, #16\n"
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".inst 0x6467e40b // bfmmla z11.s, z0.h, z7.h\n"
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".inst 0x6463e42e // bfmmla z14.s, z1.h, z3.h\n"
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".inst 0x6467e431 // bfmmla z17.s, z1.h, z7.h\n"
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".inst 0x6463e4b4 // bfmmla z20.s, z5.h, z3.h\n"
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".inst 0x6467e4b7 // bfmmla z23.s, z5.h, z7.h\n"
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".inst 0x6463e4da // bfmmla z26.s, z6.h, z3.h\n"
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".inst 0x6467e4dd // bfmmla z29.s, z6.h, z7.h\n"
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"ld1h { z3.h }, p0/Z, [x22, #-8, MUL VL]\n"
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"ld1h { z7.h }, p0/Z, [x22, #-7, MUL VL]\n"
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".inst 0x6462e409 // bfmmla z9.s, z0.h, z2.h\n"
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".inst 0x6464e40c // bfmmla z12.s, z0.h, z4.h\n"
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".inst 0x6462e42f // bfmmla z15.s, z1.h, z2.h\n"
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".inst 0x6464e432 // bfmmla z18.s, z1.h, z4.h\n"
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".inst 0x6462e4b5 // bfmmla z21.s, z5.h, z2.h\n"
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".inst 0x6464e4b8 // bfmmla z24.s, z5.h, z4.h\n"
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".inst 0x6462e4db // bfmmla z27.s, z6.h, z2.h\n"
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".inst 0x6464e4de // bfmmla z30.s, z6.h, z4.h\n"
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"ld1h { z4.h }, p0/Z, [x22, #-6, MUL VL]\n"
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".inst 0x6463e40a // bfmmla z10.s, z0.h, z3.h\n"
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".inst 0x6467e40d // bfmmla z13.s, z0.h, z7.h\n"
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"ld1rqh { z0.h }, p0/Z, [%x[Apanel], #80]\n"
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".inst 0x6463e430 // bfmmla z16.s, z1.h, z3.h\n"
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".inst 0x6467e433 // bfmmla z19.s, z1.h, z7.h\n"
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"ld1rqh { z1.h }, p0/Z, [%x[Apanel], #96]\n"
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".inst 0x6463e4b6 // bfmmla z22.s, z5.h, z3.h\n"
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".inst 0x6467e4b9 // bfmmla z25.s, z5.h, z7.h\n"
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"ld1h { z5.h }, p0/Z, [x22, #-5, MUL VL]\n"
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".inst 0x6463e4dc // bfmmla z28.s, z6.h, z3.h\n"
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".inst 0x6467e4df // bfmmla z31.s, z6.h, z7.h\n"
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"ld1rqh { z2.h }, p0/Z, [%x[Apanel], #112]\n"
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"add %x[Apanel], %x[Apanel], #0x80\n"
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"addvl x22, x22, #-4\n"
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"bge 3b\n"
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"4:"
// main loop skip
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"ld1rqh { z7.h }, p0/Z, [%x[Apanel]]\n"
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".inst 0x6464e408 // bfmmla z8.s, z0.h, z4.h\n"
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".inst 0x6465e40b // bfmmla z11.s, z0.h, z5.h\n"
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".inst 0x6464e42e // bfmmla z14.s, z1.h, z4.h\n"
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".inst 0x6465e431 // bfmmla z17.s, z1.h, z5.h\n"
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"ld1h { z6.h }, p0/Z, [x22]\n"
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".inst 0x6464e454 // bfmmla z20.s, z2.h, z4.h\n"
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".inst 0x6465e457 // bfmmla z23.s, z2.h, z5.h\n"
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"ld1h { z3.h }, p0/Z, [x22, #1, MUL VL]\n"
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".inst 0x6464e4fa // bfmmla z26.s, z7.h, z4.h\n"
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".inst 0x6465e4fd // bfmmla z29.s, z7.h, z5.h\n"
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"ld1h { z5.h }, p0/Z, [x22, #2, MUL VL]\n"
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"ld1h { z4.h }, p0/Z, [x22, #3, MUL VL]\n"
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".inst 0x6466e409 // bfmmla z9.s, z0.h, z6.h\n"
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".inst 0x6463e40c // bfmmla z12.s, z0.h, z3.h\n"
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".inst 0x6466e42f // bfmmla z15.s, z1.h, z6.h\n"
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".inst 0x6463e432 // bfmmla z18.s, z1.h, z3.h\n"
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"add %x[Apanel], %x[Apanel], #0x10\n"
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".inst 0x6466e455 // bfmmla z21.s, z2.h, z6.h\n"
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".inst 0x6463e458 // bfmmla z24.s, z2.h, z3.h\n"
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"addvl x22, x22, #4\n"
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".inst 0x6466e4fb // bfmmla z27.s, z7.h, z6.h\n"
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".inst 0x6463e4fe // bfmmla z30.s, z7.h, z3.h\n"
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".inst 0x6465e40a // bfmmla z10.s, z0.h, z5.h\n"
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".inst 0x6464e40d // bfmmla z13.s, z0.h, z4.h\n"
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".inst 0x6465e430 // bfmmla z16.s, z1.h, z5.h\n"
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".inst 0x6464e433 // bfmmla z19.s, z1.h, z4.h\n"
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".inst 0x6465e456 // bfmmla z22.s, z2.h, z5.h\n"
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".inst 0x6464e459 // bfmmla z25.s, z2.h, z4.h\n"
196
".inst 0x6465e4fc // bfmmla z28.s, z7.h, z5.h\n"
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".inst 0x6464e4ff // bfmmla z31.s, z7.h, z4.h\n"
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"cbz x20, 5f\n"
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"ld1h { z1.h }, p0/Z, [x22]\n"
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"ld1rqh { z7.h }, p0/Z, [%x[Apanel]]\n"
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".inst 0x6461e4e8 // bfmmla z8.s, z7.h, z1.h\n"
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"ld1rqh { z6.h }, p0/Z, [%x[Apanel], #16]\n"
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"ld1h { z0.h }, p0/Z, [x22, #1, MUL VL]\n"
204
".inst 0x6460e4eb // bfmmla z11.s, z7.h, z0.h\n"
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"ld1rqh { z5.h }, p0/Z, [%x[Apanel], #32]\n"
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"ld1rqh { z4.h }, p0/Z, [%x[Apanel], #48]\n"
207
".inst 0x6461e4ce // bfmmla z14.s, z6.h, z1.h\n"
208
".inst 0x6460e4d1 // bfmmla z17.s, z6.h, z0.h\n"
209
".inst 0x6461e4b4 // bfmmla z20.s, z5.h, z1.h\n"
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"ld1h { z3.h }, p0/Z, [x22, #2, MUL VL]\n"
211
".inst 0x6460e4b7 // bfmmla z23.s, z5.h, z0.h\n"
212
".inst 0x6461e49a // bfmmla z26.s, z4.h, z1.h\n"
213
"ld1h { z2.h }, p0/Z, [x22, #3, MUL VL]\n"
214
".inst 0x6460e49d // bfmmla z29.s, z4.h, z0.h\n"
215
"ld1h { z1.h }, p0/Z, [x22, #4, MUL VL]\n"
216
"ld1h { z0.h }, p0/Z, [x22, #5, MUL VL]\n"
217
".inst 0x6463e4e9 // bfmmla z9.s, z7.h, z3.h\n"
218
".inst 0x6462e4ec // bfmmla z12.s, z7.h, z2.h\n"
219
"addvl x22, x22, #6\n"
220
".inst 0x6463e4cf // bfmmla z15.s, z6.h, z3.h\n"
221
".inst 0x6462e4d2 // bfmmla z18.s, z6.h, z2.h\n"
222
"add %x[Apanel], %x[Apanel], #0x40\n"
223
".inst 0x6463e4b5 // bfmmla z21.s, z5.h, z3.h\n"
224
".inst 0x6462e4b8 // bfmmla z24.s, z5.h, z2.h\n"
225
".inst 0x6463e49b // bfmmla z27.s, z4.h, z3.h\n"
226
".inst 0x6462e49e // bfmmla z30.s, z4.h, z2.h\n"
227
".inst 0x6461e4ea // bfmmla z10.s, z7.h, z1.h\n"
228
".inst 0x6460e4ed // bfmmla z13.s, z7.h, z0.h\n"
229
".inst 0x6461e4d0 // bfmmla z16.s, z6.h, z1.h\n"
230
".inst 0x6460e4d3 // bfmmla z19.s, z6.h, z0.h\n"
231
".inst 0x6461e4b6 // bfmmla z22.s, z5.h, z1.h\n"
232
".inst 0x6460e4b9 // bfmmla z25.s, z5.h, z0.h\n"
233
".inst 0x6461e49c // bfmmla z28.s, z4.h, z1.h\n"
234
".inst 0x6460e49f // bfmmla z31.s, z4.h, z0.h\n"
235
"5:"
// multiply loop done
236
"uzp1 z0.d, z8.d, z11.d\n"
237
"uzp2 z8.d, z8.d, z11.d\n"
238
"st1w { z0.s }, p0, [%x[Cpanel]]\n"
239
"uzp1 z0.d, z9.d, z12.d\n"
240
"uzp2 z9.d, z9.d, z12.d\n"
241
"st1w { z0.s }, p0, [%x[Cpanel], #1, MUL VL]\n"
242
"uzp1 z0.d, z10.d, z13.d\n"
243
"uzp2 z10.d, z10.d, z13.d\n"
244
"st1w { z0.s }, p0, [%x[Cpanel], #2, MUL VL]\n"
245
"st1w { z8.s }, p0, [%x[Cpanel], #3, MUL VL]\n"
246
"uzp1 z0.d, z14.d, z17.d\n"
247
"uzp2 z14.d, z14.d, z17.d\n"
248
"st1w { z9.s }, p0, [%x[Cpanel], #4, MUL VL]\n"
249
"uzp1 z1.d, z15.d, z18.d\n"
250
"subs x23, x23, #0x1\n"
251
"st1w { z10.s }, p0, [%x[Cpanel], #5, MUL VL]\n"
252
"uzp2 z15.d, z15.d, z18.d\n"
253
"uzp1 z17.d, z16.d, z19.d\n"
254
"st1w { z0.s }, p0, [%x[Cpanel], #6, MUL VL]\n"
255
"uzp2 z16.d, z16.d, z19.d\n"
256
"uzp1 z0.d, z20.d, z23.d\n"
257
"st1w { z1.s }, p0, [%x[Cpanel], #7, MUL VL]\n"
258
"addvl %x[Cpanel], %x[Cpanel], #16\n"
259
"uzp2 z20.d, z20.d, z23.d\n"
260
"st1w { z17.s }, p0, [%x[Cpanel], #-8, MUL VL]\n"
261
"uzp1 z23.d, z21.d, z24.d\n"
262
"uzp2 z21.d, z21.d, z24.d\n"
263
"st1w { z14.s }, p0, [%x[Cpanel], #-7, MUL VL]\n"
264
"uzp1 z19.d, z22.d, z25.d\n"
265
"uzp2 z22.d, z22.d, z25.d\n"
266
"st1w { z15.s }, p0, [%x[Cpanel], #-6, MUL VL]\n"
267
"uzp1 z18.d, z26.d, z29.d\n"
268
"uzp2 z26.d, z26.d, z29.d\n"
269
"st1w { z16.s }, p0, [%x[Cpanel], #-5, MUL VL]\n"
270
"uzp1 z17.d, z27.d, z30.d\n"
271
"uzp2 z27.d, z27.d, z30.d\n"
272
"st1w { z0.s }, p0, [%x[Cpanel], #-4, MUL VL]\n"
273
"uzp1 z16.d, z28.d, z31.d\n"
274
"uzp2 z28.d, z28.d, z31.d\n"
275
"st1w { z23.s }, p0, [%x[Cpanel], #-3, MUL VL]\n"
276
"st1w { z19.s }, p0, [%x[Cpanel], #-2, MUL VL]\n"
277
"st1w { z20.s }, p0, [%x[Cpanel], #-1, MUL VL]\n"
278
"st1w { z21.s }, p0, [%x[Cpanel]]\n"
279
"st1w { z22.s }, p0, [%x[Cpanel], #1, MUL VL]\n"
280
"st1w { z18.s }, p0, [%x[Cpanel], #2, MUL VL]\n"
281
"st1w { z17.s }, p0, [%x[Cpanel], #3, MUL VL]\n"
282
"st1w { z16.s }, p0, [%x[Cpanel], #4, MUL VL]\n"
283
"st1w { z26.s }, p0, [%x[Cpanel], #5, MUL VL]\n"
284
"st1w { z27.s }, p0, [%x[Cpanel], #6, MUL VL]\n"
285
"st1w { z28.s }, p0, [%x[Cpanel], #7, MUL VL]\n"
286
"addvl %x[Cpanel], %x[Cpanel], #8\n"
287
"bgt 2b\n"
288
"subs %x[ablocks], %x[ablocks], #0x1\n"
289
"bne 1b\n"
290
: [Apanel]
"+&r"
(Apanel), [Cpanel]
"+&r"
(Cpanel), [ablocks]
"+&r"
(ablocks)
291
: [args_ptr]
"r"
(&ka), [offsetof_Bpanel]
"I"
(offsetof(KernelArgs, Bpanel)), [offsetof_K]
"I"
(offsetof(KernelArgs,
K
)), [offsetof_bblocks]
"I"
(offsetof(KernelArgs, bblocks))
292
:
"cc"
,
"memory"
,
"p0"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"z0"
,
"z1"
,
"z2"
,
"z3"
,
"z4"
,
"z5"
,
"z6"
,
"z7"
,
"z8"
,
"z9"
,
"z10"
,
"z11"
,
"z12"
,
"z13"
,
"z14"
,
"z15"
,
"z16"
,
"z17"
,
"z18"
,
"z19"
,
"z20"
,
"z21"
,
"z22"
,
"z23"
,
"z24"
,
"z25"
,
"z26"
,
"z27"
,
"z28"
,
"z29"
,
"z30"
,
"z31"
293
);
294
}
295
296
}
// namespace arm_gemm
297
#endif // ARM_COMPUTE_ENABLE_SVE
arm_gemm
Definition:
barrier.hpp:30
arm_gemm::bfloat16
arm_compute::bfloat16 bfloat16
Definition:
bfloat.hpp:30
K
unsigned int K
Definition:
CpuGemmAssemblyDispatch.cpp:106
src
core
NEON
kernels
arm_gemm
kernels
sve_interleaved_bf16fp32_mmla_8x3VL
generic.cpp
Generated on Mon Apr 29 2024 10:53:55 for Compute Library by
1.8.17