24.02.1
fp16.cpp
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/*
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* Copyright (c) 2022-2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
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#include "
src/cpu/CpuTypes.h
"
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#include "
src/cpu/kernels/depthwiseconv2d/generic/neon/impl.h
"
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namespace
arm_compute
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{
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namespace
cpu
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{
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void
neon_fp16_deptwiseconv2dnative
(
const
ITensor *
src
,
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const
ITensor *weights,
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const
ITensor *
bias
,
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ITensor *
dst
,
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const
Window &window,
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bool
has_biases,
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const
ConvolutionInfo &
info
)
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{
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return
run_depthwise_float<float16_t, float16_t>(
src
, weights,
bias
,
dst
, window, has_biases,
info
);
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}
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}
// namespace cpu
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}
// namespace arm_compute
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#endif //__ARM_FEATURE_FP16_VECTOR_ARITHMETIC
arm_compute::test::validation::src
SimpleTensor< float > src
Definition:
DFT.cpp:155
arm_compute::test::validation::dst
auto dst
Definition:
DFT.cpp:170
CpuTypes.h
bias
const int32_t * bias
Definition:
working_space.hpp:322
impl.h
arm_compute::cpu::neon_fp16_deptwiseconv2dnative
void neon_fp16_deptwiseconv2dnative(const ITensor *src, const ITensor *weights, const ITensor *bias, ITensor *dst, const Window &window, bool has_biases, const ConvolutionInfo &info)
arm_compute
Copyright (c) 2017-2024 Arm Limited.
Definition:
introduction.dox:24
arm_compute::test::validation::info
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
src
cpu
kernels
depthwiseconv2d
generic
neon
fp16.cpp
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