Compute Library
 21.02
list.h
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1 /*
2  * Copyright (c) 2021 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
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24 #ifndef SRC_CORE_NEON_KERNELS_POOLING_LIST_H
25 #define SRC_CORE_NEON_KERNELS_POOLING_LIST_H
26 
27 #include "arm_compute/core/Types.h"
31 #include <arm_neon.h>
32 
33 namespace arm_compute
34 {
35 namespace cpu
36 {
37 #define DECLARE_POOLING_KERNEL(func_name) \
38  void func_name(const ITensor *src0, ITensor *dst0, ITensor *dst1, PoolingLayerInfo &, const Window &window_src, const Window &window)
39 
44 
45 #if defined(ENABLE_NCHW_KERNELS)
46 
47 #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS)
48 DECLARE_POOLING_KERNEL(pooling2_fp16_neon_nchw);
49 DECLARE_POOLING_KERNEL(pooling3_fp16_neon_nchw);
50 DECLARE_POOLING_KERNEL(poolingMxN_fp16_neon_nchw);
51 #endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */
52 
53 DECLARE_POOLING_KERNEL(pooling2_fp32_neon_nchw);
54 DECLARE_POOLING_KERNEL(pooling3_fp32_neon_nchw);
55 DECLARE_POOLING_KERNEL(pooling7_fp32_neon_nchw);
56 DECLARE_POOLING_KERNEL(poolingMxN_fp32_neon_nchw);
57 #endif /* defined(ENABLE_NCHW_KERNELS) */
58 
59 #undef DECLARE_POOLING_KERNEL
60 
61 template <typename T>
62 inline uint32_t offset_no_padding(uint32_t padded_offset, const Coordinates &id, const ITensorInfo &info, int pool_stride_x, int pool_stride_y)
63 {
64  const int pad_left = info.padding().left;
65  const int pad_right = info.padding().right;
66  const int pad_top = info.padding().top;
67  const int pad_bottom = info.padding().bottom;
68  const int in_stride_y = static_cast<int>(info.strides_in_bytes().y());
69  const int in_stride_w = static_cast<int>(info.strides_in_bytes()[3]);
70  const int pad_horiz = pad_left + pad_right;
71  const int pad_vert = pad_top + pad_bottom;
72 
73  if(info.data_layout() == DataLayout::NCHW)
74  {
75  const uint32_t offset_base = padded_offset
76  - sizeof(T) * pad_horiz * id.y() * pool_stride_y /* subtract padding elems per row */
77  - pad_top * sizeof(T) /* top padding */
78  - sizeof(T) * pad_horiz * info.tensor_shape()[1] * id.z() - pad_vert * in_stride_y * id.z() /* for each Z plane there are height*pad_right padding elems */
79  - in_stride_w * id[3];
80 
81  return offset_base;
82  }
83  else
84  {
85  const uint32_t offset_base = padded_offset
86  - sizeof(T) * pad_horiz * id.y() * pool_stride_x // subtract padding elems per row
87  - pad_top * sizeof(T) // top padding
88  - sizeof(T) * pad_horiz * info.tensor_shape()[1] * id.z() * pool_stride_y // for each Z plane there are width*pad_right padding elems
89  - in_stride_w * id[3];
90 
91  return offset_base;
92  }
93 }
94 } // namespace cpu
95 } // namespace arm_compute
96 
97 #endif // SRC_CORE_NEON_KERNELS_POOLING_LIST_H
unsigned int top
top of the border
Definition: Types.h:375
void poolingMxN_qasymm8_neon_nhwc(const ITensor *src0, ITensor *dst0, ITensor *dst1, PoolingLayerInfo &, const Window &window_src, const Window &window)
Definition: qasymm8.cpp:36
void poolingMxN_fp32_neon_nhwc(const ITensor *src, ITensor *dst0, ITensor *dst1, PoolingLayerInfo &pool_info, const Window &window_src, const Window &window)
Definition: fp32.cpp:144
Store the tensor&#39;s metadata.
Definition: ITensorInfo.h:40
unsigned int bottom
bottom of the border
Definition: Types.h:377
int pool_stride_x
Copyright (c) 2017-2021 Arm Limited.
virtual const TensorShape & tensor_shape() const =0
Size for each dimension of the tensor.
T z() const
Alias to access the size of the third dimension.
Definition: Dimensions.h:97
Coordinates of an item.
Definition: Coordinates.h:37
#define DECLARE_POOLING_KERNEL(func_name)
Definition: list.h:37
uint32_t offset_no_padding(uint32_t padded_offset, const Coordinates &id, const ITensorInfo &info, int pool_stride_x, int pool_stride_y)
Definition: list.h:62
void poolingMxN_fp16_neon_nhwc(const ITensor *src0, ITensor *dst0, ITensor *dst1, PoolingLayerInfo &, const Window &window_src, const Window &window)
virtual PaddingSize padding() const =0
Padding of tensor.
unsigned int left
left of the border
Definition: Types.h:378
unsigned int right
right of the border
Definition: Types.h:376
Num samples, channels, height, width.
ScaleKernelInfo info(interpolation_policy, default_border_mode, PixelValue(), sampling_policy, false)
void poolingMxN_qasymm8_signed_neon_nhwc(const ITensor *src0, ITensor *dst0, ITensor *dst1, PoolingLayerInfo &, const Window &window_src, const Window &window)
T y() const
Alias to access the size of the second dimension.
Definition: Dimensions.h:92
Includes all wrapper headers at once.
virtual const Strides & strides_in_bytes() const =0
The strides in bytes for accessing each dimension of the tensor.
virtual DataLayout data_layout() const =0
Get the data layout of the tensor.