Compute Library
 21.05
hwc_names.hpp
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1 /*
2  * Copyright (c) 2017-2021 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to
8  * deal in the Software without restriction, including without limitation the
9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10  * sell copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in all
14  * copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 #ifndef ARM_COMPUTE_TEST_HWC_NAMES
25 #define ARM_COMPUTE_TEST_HWC_NAMES
26 
27 #ifndef DOXYGEN_SKIP_THIS
28 
29 namespace mali_userspace
30 {
31 enum MaliCounterBlockName
32 {
33  MALI_NAME_BLOCK_JM = 0,
34  MALI_NAME_BLOCK_TILER = 1,
35  MALI_NAME_BLOCK_SHADER = 2,
36  MALI_NAME_BLOCK_MMU = 3
37 };
38 
39 enum
40 {
41  MALI_NAME_BLOCK_SIZE = 64
42 };
43 
44 /*
45  * "Short names" for hardware counters used by Streamline. Counters names are
46  * stored in accordance with their memory layout in the binary counter block
47  * emitted by the Arm® Mali™ GPU. Each "master" in the GPU emits a fixed-size block
48  * of 64 counters, and each GPU implements the same set of "masters" although
49  * the counters each master exposes within its block of 64 may vary.
50  *
51  * Counters which are an empty string are simply "holes" in the counter memory
52  * where no counter exists.
53  */
54 
55 static const char *const hardware_counters_mali_t60x[] =
56 {
57  /* Job Manager */
58  "",
59  "",
60  "",
61  "",
62  "T60x_MESSAGES_SENT",
63  "T60x_MESSAGES_RECEIVED",
64  "T60x_GPU_ACTIVE",
65  "T60x_IRQ_ACTIVE",
66  "T60x_JS0_JOBS",
67  "T60x_JS0_TASKS",
68  "T60x_JS0_ACTIVE",
69  "",
70  "T60x_JS0_WAIT_READ",
71  "T60x_JS0_WAIT_ISSUE",
72  "T60x_JS0_WAIT_DEPEND",
73  "T60x_JS0_WAIT_FINISH",
74  "T60x_JS1_JOBS",
75  "T60x_JS1_TASKS",
76  "T60x_JS1_ACTIVE",
77  "",
78  "T60x_JS1_WAIT_READ",
79  "T60x_JS1_WAIT_ISSUE",
80  "T60x_JS1_WAIT_DEPEND",
81  "T60x_JS1_WAIT_FINISH",
82  "T60x_JS2_JOBS",
83  "T60x_JS2_TASKS",
84  "T60x_JS2_ACTIVE",
85  "",
86  "T60x_JS2_WAIT_READ",
87  "T60x_JS2_WAIT_ISSUE",
88  "T60x_JS2_WAIT_DEPEND",
89  "T60x_JS2_WAIT_FINISH",
90  "",
91  "",
92  "",
93  "",
94  "",
95  "",
96  "",
97  "",
98  "",
99  "",
100  "",
101  "",
102  "",
103  "",
104  "",
105  "",
106  "",
107  "",
108  "",
109  "",
110  "",
111  "",
112  "",
113  "",
114  "",
115  "",
116  "",
117  "",
118  "",
119  "",
120  "",
121  "",
122 
123  /*Tiler */
124  "",
125  "",
126  "",
127  "T60x_TI_JOBS_PROCESSED",
128  "T60x_TI_TRIANGLES",
129  "T60x_TI_QUADS",
130  "T60x_TI_POLYGONS",
131  "T60x_TI_POINTS",
132  "T60x_TI_LINES",
133  "T60x_TI_VCACHE_HIT",
134  "T60x_TI_VCACHE_MISS",
135  "T60x_TI_FRONT_FACING",
136  "T60x_TI_BACK_FACING",
137  "T60x_TI_PRIM_VISIBLE",
138  "T60x_TI_PRIM_CULLED",
139  "T60x_TI_PRIM_CLIPPED",
140  "T60x_TI_LEVEL0",
141  "T60x_TI_LEVEL1",
142  "T60x_TI_LEVEL2",
143  "T60x_TI_LEVEL3",
144  "T60x_TI_LEVEL4",
145  "T60x_TI_LEVEL5",
146  "T60x_TI_LEVEL6",
147  "T60x_TI_LEVEL7",
148  "T60x_TI_COMMAND_1",
149  "T60x_TI_COMMAND_2",
150  "T60x_TI_COMMAND_3",
151  "T60x_TI_COMMAND_4",
152  "T60x_TI_COMMAND_4_7",
153  "T60x_TI_COMMAND_8_15",
154  "T60x_TI_COMMAND_16_63",
155  "T60x_TI_COMMAND_64",
156  "T60x_TI_COMPRESS_IN",
157  "T60x_TI_COMPRESS_OUT",
158  "T60x_TI_COMPRESS_FLUSH",
159  "T60x_TI_TIMESTAMPS",
160  "T60x_TI_PCACHE_HIT",
161  "T60x_TI_PCACHE_MISS",
162  "T60x_TI_PCACHE_LINE",
163  "T60x_TI_PCACHE_STALL",
164  "T60x_TI_WRBUF_HIT",
165  "T60x_TI_WRBUF_MISS",
166  "T60x_TI_WRBUF_LINE",
167  "T60x_TI_WRBUF_PARTIAL",
168  "T60x_TI_WRBUF_STALL",
169  "T60x_TI_ACTIVE",
170  "T60x_TI_LOADING_DESC",
171  "T60x_TI_INDEX_WAIT",
172  "T60x_TI_INDEX_RANGE_WAIT",
173  "T60x_TI_VERTEX_WAIT",
174  "T60x_TI_PCACHE_WAIT",
175  "T60x_TI_WRBUF_WAIT",
176  "T60x_TI_BUS_READ",
177  "T60x_TI_BUS_WRITE",
178  "",
179  "",
180  "",
181  "",
182  "",
183  "T60x_TI_UTLB_STALL",
184  "T60x_TI_UTLB_REPLAY_MISS",
185  "T60x_TI_UTLB_REPLAY_FULL",
186  "T60x_TI_UTLB_NEW_MISS",
187  "T60x_TI_UTLB_HIT",
188 
189  /* Shader Core */
190  "",
191  "",
192  "",
193  "",
194  "T60x_FRAG_ACTIVE",
195  "T60x_FRAG_PRIMITIVES",
196  "T60x_FRAG_PRIMITIVES_DROPPED",
197  "T60x_FRAG_CYCLES_DESC",
198  "T60x_FRAG_CYCLES_PLR",
199  "T60x_FRAG_CYCLES_VERT",
200  "T60x_FRAG_CYCLES_TRISETUP",
201  "T60x_FRAG_CYCLES_RAST",
202  "T60x_FRAG_THREADS",
203  "T60x_FRAG_DUMMY_THREADS",
204  "T60x_FRAG_QUADS_RAST",
205  "T60x_FRAG_QUADS_EZS_TEST",
206  "T60x_FRAG_QUADS_EZS_KILLED",
207  "T60x_FRAG_THREADS_LZS_TEST",
208  "T60x_FRAG_THREADS_LZS_KILLED",
209  "T60x_FRAG_CYCLES_NO_TILE",
210  "T60x_FRAG_NUM_TILES",
211  "T60x_FRAG_TRANS_ELIM",
212  "T60x_COMPUTE_ACTIVE",
213  "T60x_COMPUTE_TASKS",
214  "T60x_COMPUTE_THREADS",
215  "T60x_COMPUTE_CYCLES_DESC",
216  "T60x_TRIPIPE_ACTIVE",
217  "T60x_ARITH_WORDS",
218  "T60x_ARITH_CYCLES_REG",
219  "T60x_ARITH_CYCLES_L0",
220  "T60x_ARITH_FRAG_DEPEND",
221  "T60x_LS_WORDS",
222  "T60x_LS_ISSUES",
223  "T60x_LS_RESTARTS",
224  "T60x_LS_REISSUES_MISS",
225  "T60x_LS_REISSUES_VD",
226  "T60x_LS_REISSUE_ATTRIB_MISS",
227  "T60x_LS_NO_WB",
228  "T60x_TEX_WORDS",
229  "T60x_TEX_BUBBLES",
230  "T60x_TEX_WORDS_L0",
231  "T60x_TEX_WORDS_DESC",
232  "T60x_TEX_ISSUES",
233  "T60x_TEX_RECIRC_FMISS",
234  "T60x_TEX_RECIRC_DESC",
235  "T60x_TEX_RECIRC_MULTI",
236  "T60x_TEX_RECIRC_PMISS",
237  "T60x_TEX_RECIRC_CONF",
238  "T60x_LSC_READ_HITS",
239  "T60x_LSC_READ_MISSES",
240  "T60x_LSC_WRITE_HITS",
241  "T60x_LSC_WRITE_MISSES",
242  "T60x_LSC_ATOMIC_HITS",
243  "T60x_LSC_ATOMIC_MISSES",
244  "T60x_LSC_LINE_FETCHES",
245  "T60x_LSC_DIRTY_LINE",
246  "T60x_LSC_SNOOPS",
247  "T60x_AXI_TLB_STALL",
248  "T60x_AXI_TLB_MISS",
249  "T60x_AXI_TLB_TRANSACTION",
250  "T60x_LS_TLB_MISS",
251  "T60x_LS_TLB_HIT",
252  "T60x_AXI_BEATS_READ",
253  "T60x_AXI_BEATS_WRITTEN",
254 
255  /*L2 and MMU */
256  "",
257  "",
258  "",
259  "",
260  "T60x_MMU_HIT",
261  "T60x_MMU_NEW_MISS",
262  "T60x_MMU_REPLAY_FULL",
263  "T60x_MMU_REPLAY_MISS",
264  "T60x_MMU_TABLE_WALK",
265  "",
266  "",
267  "",
268  "",
269  "",
270  "",
271  "",
272  "T60x_UTLB_HIT",
273  "T60x_UTLB_NEW_MISS",
274  "T60x_UTLB_REPLAY_FULL",
275  "T60x_UTLB_REPLAY_MISS",
276  "T60x_UTLB_STALL",
277  "",
278  "",
279  "",
280  "",
281  "",
282  "",
283  "",
284  "",
285  "",
286  "T60x_L2_EXT_WRITE_BEATS",
287  "T60x_L2_EXT_READ_BEATS",
288  "T60x_L2_ANY_LOOKUP",
289  "T60x_L2_READ_LOOKUP",
290  "T60x_L2_SREAD_LOOKUP",
291  "T60x_L2_READ_REPLAY",
292  "T60x_L2_READ_SNOOP",
293  "T60x_L2_READ_HIT",
294  "T60x_L2_CLEAN_MISS",
295  "T60x_L2_WRITE_LOOKUP",
296  "T60x_L2_SWRITE_LOOKUP",
297  "T60x_L2_WRITE_REPLAY",
298  "T60x_L2_WRITE_SNOOP",
299  "T60x_L2_WRITE_HIT",
300  "T60x_L2_EXT_READ_FULL",
301  "T60x_L2_EXT_READ_HALF",
302  "T60x_L2_EXT_WRITE_FULL",
303  "T60x_L2_EXT_WRITE_HALF",
304  "T60x_L2_EXT_READ",
305  "T60x_L2_EXT_READ_LINE",
306  "T60x_L2_EXT_WRITE",
307  "T60x_L2_EXT_WRITE_LINE",
308  "T60x_L2_EXT_WRITE_SMALL",
309  "T60x_L2_EXT_BARRIER",
310  "T60x_L2_EXT_AR_STALL",
311  "T60x_L2_EXT_R_BUF_FULL",
312  "T60x_L2_EXT_RD_BUF_FULL",
313  "T60x_L2_EXT_R_RAW",
314  "T60x_L2_EXT_W_STALL",
315  "T60x_L2_EXT_W_BUF_FULL",
316  "T60x_L2_EXT_R_W_HAZARD",
317  "T60x_L2_TAG_HAZARD",
318  "T60x_L2_SNOOP_FULL",
319  "T60x_L2_REPLAY_FULL"
320 };
321 static const char *const hardware_counters_mali_t62x[] =
322 {
323  /* Job Manager */
324  "",
325  "",
326  "",
327  "",
328  "T62x_MESSAGES_SENT",
329  "T62x_MESSAGES_RECEIVED",
330  "T62x_GPU_ACTIVE",
331  "T62x_IRQ_ACTIVE",
332  "T62x_JS0_JOBS",
333  "T62x_JS0_TASKS",
334  "T62x_JS0_ACTIVE",
335  "",
336  "T62x_JS0_WAIT_READ",
337  "T62x_JS0_WAIT_ISSUE",
338  "T62x_JS0_WAIT_DEPEND",
339  "T62x_JS0_WAIT_FINISH",
340  "T62x_JS1_JOBS",
341  "T62x_JS1_TASKS",
342  "T62x_JS1_ACTIVE",
343  "",
344  "T62x_JS1_WAIT_READ",
345  "T62x_JS1_WAIT_ISSUE",
346  "T62x_JS1_WAIT_DEPEND",
347  "T62x_JS1_WAIT_FINISH",
348  "T62x_JS2_JOBS",
349  "T62x_JS2_TASKS",
350  "T62x_JS2_ACTIVE",
351  "",
352  "T62x_JS2_WAIT_READ",
353  "T62x_JS2_WAIT_ISSUE",
354  "T62x_JS2_WAIT_DEPEND",
355  "T62x_JS2_WAIT_FINISH",
356  "",
357  "",
358  "",
359  "",
360  "",
361  "",
362  "",
363  "",
364  "",
365  "",
366  "",
367  "",
368  "",
369  "",
370  "",
371  "",
372  "",
373  "",
374  "",
375  "",
376  "",
377  "",
378  "",
379  "",
380  "",
381  "",
382  "",
383  "",
384  "",
385  "",
386  "",
387  "",
388 
389  /*Tiler */
390  "",
391  "",
392  "",
393  "T62x_TI_JOBS_PROCESSED",
394  "T62x_TI_TRIANGLES",
395  "T62x_TI_QUADS",
396  "T62x_TI_POLYGONS",
397  "T62x_TI_POINTS",
398  "T62x_TI_LINES",
399  "T62x_TI_VCACHE_HIT",
400  "T62x_TI_VCACHE_MISS",
401  "T62x_TI_FRONT_FACING",
402  "T62x_TI_BACK_FACING",
403  "T62x_TI_PRIM_VISIBLE",
404  "T62x_TI_PRIM_CULLED",
405  "T62x_TI_PRIM_CLIPPED",
406  "T62x_TI_LEVEL0",
407  "T62x_TI_LEVEL1",
408  "T62x_TI_LEVEL2",
409  "T62x_TI_LEVEL3",
410  "T62x_TI_LEVEL4",
411  "T62x_TI_LEVEL5",
412  "T62x_TI_LEVEL6",
413  "T62x_TI_LEVEL7",
414  "T62x_TI_COMMAND_1",
415  "T62x_TI_COMMAND_2",
416  "T62x_TI_COMMAND_3",
417  "T62x_TI_COMMAND_4",
418  "T62x_TI_COMMAND_5_7",
419  "T62x_TI_COMMAND_8_15",
420  "T62x_TI_COMMAND_16_63",
421  "T62x_TI_COMMAND_64",
422  "T62x_TI_COMPRESS_IN",
423  "T62x_TI_COMPRESS_OUT",
424  "T62x_TI_COMPRESS_FLUSH",
425  "T62x_TI_TIMESTAMPS",
426  "T62x_TI_PCACHE_HIT",
427  "T62x_TI_PCACHE_MISS",
428  "T62x_TI_PCACHE_LINE",
429  "T62x_TI_PCACHE_STALL",
430  "T62x_TI_WRBUF_HIT",
431  "T62x_TI_WRBUF_MISS",
432  "T62x_TI_WRBUF_LINE",
433  "T62x_TI_WRBUF_PARTIAL",
434  "T62x_TI_WRBUF_STALL",
435  "T62x_TI_ACTIVE",
436  "T62x_TI_LOADING_DESC",
437  "T62x_TI_INDEX_WAIT",
438  "T62x_TI_INDEX_RANGE_WAIT",
439  "T62x_TI_VERTEX_WAIT",
440  "T62x_TI_PCACHE_WAIT",
441  "T62x_TI_WRBUF_WAIT",
442  "T62x_TI_BUS_READ",
443  "T62x_TI_BUS_WRITE",
444  "",
445  "",
446  "",
447  "",
448  "",
449  "T62x_TI_UTLB_STALL",
450  "T62x_TI_UTLB_REPLAY_MISS",
451  "T62x_TI_UTLB_REPLAY_FULL",
452  "T62x_TI_UTLB_NEW_MISS",
453  "T62x_TI_UTLB_HIT",
454 
455  /* Shader Core */
456  "",
457  "",
458  "",
459  "T62x_SHADER_CORE_ACTIVE",
460  "T62x_FRAG_ACTIVE",
461  "T62x_FRAG_PRIMITIVES",
462  "T62x_FRAG_PRIMITIVES_DROPPED",
463  "T62x_FRAG_CYCLES_DESC",
464  "T62x_FRAG_CYCLES_FPKQ_ACTIVE",
465  "T62x_FRAG_CYCLES_VERT",
466  "T62x_FRAG_CYCLES_TRISETUP",
467  "T62x_FRAG_CYCLES_EZS_ACTIVE",
468  "T62x_FRAG_THREADS",
469  "T62x_FRAG_DUMMY_THREADS",
470  "T62x_FRAG_QUADS_RAST",
471  "T62x_FRAG_QUADS_EZS_TEST",
472  "T62x_FRAG_QUADS_EZS_KILLED",
473  "T62x_FRAG_THREADS_LZS_TEST",
474  "T62x_FRAG_THREADS_LZS_KILLED",
475  "T62x_FRAG_CYCLES_NO_TILE",
476  "T62x_FRAG_NUM_TILES",
477  "T62x_FRAG_TRANS_ELIM",
478  "T62x_COMPUTE_ACTIVE",
479  "T62x_COMPUTE_TASKS",
480  "T62x_COMPUTE_THREADS",
481  "T62x_COMPUTE_CYCLES_DESC",
482  "T62x_TRIPIPE_ACTIVE",
483  "T62x_ARITH_WORDS",
484  "T62x_ARITH_CYCLES_REG",
485  "T62x_ARITH_CYCLES_L0",
486  "T62x_ARITH_FRAG_DEPEND",
487  "T62x_LS_WORDS",
488  "T62x_LS_ISSUES",
489  "T62x_LS_RESTARTS",
490  "T62x_LS_REISSUES_MISS",
491  "T62x_LS_REISSUES_VD",
492  "T62x_LS_REISSUE_ATTRIB_MISS",
493  "T62x_LS_NO_WB",
494  "T62x_TEX_WORDS",
495  "T62x_TEX_BUBBLES",
496  "T62x_TEX_WORDS_L0",
497  "T62x_TEX_WORDS_DESC",
498  "T62x_TEX_ISSUES",
499  "T62x_TEX_RECIRC_FMISS",
500  "T62x_TEX_RECIRC_DESC",
501  "T62x_TEX_RECIRC_MULTI",
502  "T62x_TEX_RECIRC_PMISS",
503  "T62x_TEX_RECIRC_CONF",
504  "T62x_LSC_READ_HITS",
505  "T62x_LSC_READ_MISSES",
506  "T62x_LSC_WRITE_HITS",
507  "T62x_LSC_WRITE_MISSES",
508  "T62x_LSC_ATOMIC_HITS",
509  "T62x_LSC_ATOMIC_MISSES",
510  "T62x_LSC_LINE_FETCHES",
511  "T62x_LSC_DIRTY_LINE",
512  "T62x_LSC_SNOOPS",
513  "T62x_AXI_TLB_STALL",
514  "T62x_AXI_TLB_MISS",
515  "T62x_AXI_TLB_TRANSACTION",
516  "T62x_LS_TLB_MISS",
517  "T62x_LS_TLB_HIT",
518  "T62x_AXI_BEATS_READ",
519  "T62x_AXI_BEATS_WRITTEN",
520 
521  /*L2 and MMU */
522  "",
523  "",
524  "",
525  "",
526  "T62x_MMU_HIT",
527  "T62x_MMU_NEW_MISS",
528  "T62x_MMU_REPLAY_FULL",
529  "T62x_MMU_REPLAY_MISS",
530  "T62x_MMU_TABLE_WALK",
531  "",
532  "",
533  "",
534  "",
535  "",
536  "",
537  "",
538  "T62x_UTLB_HIT",
539  "T62x_UTLB_NEW_MISS",
540  "T62x_UTLB_REPLAY_FULL",
541  "T62x_UTLB_REPLAY_MISS",
542  "T62x_UTLB_STALL",
543  "",
544  "",
545  "",
546  "",
547  "",
548  "",
549  "",
550  "",
551  "",
552  "T62x_L2_EXT_WRITE_BEATS",
553  "T62x_L2_EXT_READ_BEATS",
554  "T62x_L2_ANY_LOOKUP",
555  "T62x_L2_READ_LOOKUP",
556  "T62x_L2_SREAD_LOOKUP",
557  "T62x_L2_READ_REPLAY",
558  "T62x_L2_READ_SNOOP",
559  "T62x_L2_READ_HIT",
560  "T62x_L2_CLEAN_MISS",
561  "T62x_L2_WRITE_LOOKUP",
562  "T62x_L2_SWRITE_LOOKUP",
563  "T62x_L2_WRITE_REPLAY",
564  "T62x_L2_WRITE_SNOOP",
565  "T62x_L2_WRITE_HIT",
566  "T62x_L2_EXT_READ_FULL",
567  "T62x_L2_EXT_READ_HALF",
568  "T62x_L2_EXT_WRITE_FULL",
569  "T62x_L2_EXT_WRITE_HALF",
570  "T62x_L2_EXT_READ",
571  "T62x_L2_EXT_READ_LINE",
572  "T62x_L2_EXT_WRITE",
573  "T62x_L2_EXT_WRITE_LINE",
574  "T62x_L2_EXT_WRITE_SMALL",
575  "T62x_L2_EXT_BARRIER",
576  "T62x_L2_EXT_AR_STALL",
577  "T62x_L2_EXT_R_BUF_FULL",
578  "T62x_L2_EXT_RD_BUF_FULL",
579  "T62x_L2_EXT_R_RAW",
580  "T62x_L2_EXT_W_STALL",
581  "T62x_L2_EXT_W_BUF_FULL",
582  "T62x_L2_EXT_R_W_HAZARD",
583  "T62x_L2_TAG_HAZARD",
584  "T62x_L2_SNOOP_FULL",
585  "T62x_L2_REPLAY_FULL"
586 };
587 
588 static const char *const hardware_counters_mali_t72x[] =
589 {
590  /* Job Manager */
591  "",
592  "",
593  "",
594  "",
595  "T72x_GPU_ACTIVE",
596  "T72x_IRQ_ACTIVE",
597  "T72x_JS0_JOBS",
598  "T72x_JS0_TASKS",
599  "T72x_JS0_ACTIVE",
600  "T72x_JS1_JOBS",
601  "T72x_JS1_TASKS",
602  "T72x_JS1_ACTIVE",
603  "T72x_JS2_JOBS",
604  "T72x_JS2_TASKS",
605  "T72x_JS2_ACTIVE",
606  "",
607  "",
608  "",
609  "",
610  "",
611  "",
612  "",
613  "",
614  "",
615  "",
616  "",
617  "",
618  "",
619  "",
620  "",
621  "",
622  "",
623  "",
624  "",
625  "",
626  "",
627  "",
628  "",
629  "",
630  "",
631  "",
632  "",
633  "",
634  "",
635  "",
636  "",
637  "",
638  "",
639  "",
640  "",
641  "",
642  "",
643  "",
644  "",
645  "",
646  "",
647  "",
648  "",
649  "",
650  "",
651  "",
652  "",
653  "",
654  "",
655 
656  /*Tiler */
657  "",
658  "",
659  "",
660  "T72x_TI_JOBS_PROCESSED",
661  "T72x_TI_TRIANGLES",
662  "T72x_TI_QUADS",
663  "T72x_TI_POLYGONS",
664  "T72x_TI_POINTS",
665  "T72x_TI_LINES",
666  "T72x_TI_FRONT_FACING",
667  "T72x_TI_BACK_FACING",
668  "T72x_TI_PRIM_VISIBLE",
669  "T72x_TI_PRIM_CULLED",
670  "T72x_TI_PRIM_CLIPPED",
671  "",
672  "",
673  "",
674  "",
675  "",
676  "",
677  "",
678  "",
679  "T72x_TI_ACTIVE",
680  "",
681  "",
682  "",
683  "",
684  "",
685  "",
686  "",
687  "",
688  "",
689  "",
690  "",
691  "",
692  "",
693  "",
694  "",
695  "",
696  "",
697  "",
698  "",
699  "",
700  "",
701  "",
702  "",
703  "",
704  "",
705  "",
706  "",
707  "",
708  "",
709  "",
710  "",
711  "",
712  "",
713  "",
714  "",
715  "",
716  "",
717  "",
718  "",
719  "",
720  "",
721 
722  /* Shader Core */
723  "",
724  "",
725  "",
726  "",
727  "T72x_FRAG_ACTIVE",
728  "T72x_FRAG_PRIMITIVES",
729  "T72x_FRAG_PRIMITIVES_DROPPED",
730  "T72x_FRAG_THREADS",
731  "T72x_FRAG_DUMMY_THREADS",
732  "T72x_FRAG_QUADS_RAST",
733  "T72x_FRAG_QUADS_EZS_TEST",
734  "T72x_FRAG_QUADS_EZS_KILLED",
735  "T72x_FRAG_THREADS_LZS_TEST",
736  "T72x_FRAG_THREADS_LZS_KILLED",
737  "T72x_FRAG_CYCLES_NO_TILE",
738  "T72x_FRAG_NUM_TILES",
739  "T72x_FRAG_TRANS_ELIM",
740  "T72x_COMPUTE_ACTIVE",
741  "T72x_COMPUTE_TASKS",
742  "T72x_COMPUTE_THREADS",
743  "T72x_TRIPIPE_ACTIVE",
744  "T72x_ARITH_WORDS",
745  "T72x_ARITH_CYCLES_REG",
746  "T72x_LS_WORDS",
747  "T72x_LS_ISSUES",
748  "T72x_LS_RESTARTS",
749  "T72x_LS_REISSUES_MISS",
750  "T72x_TEX_WORDS",
751  "T72x_TEX_BUBBLES",
752  "T72x_TEX_ISSUES",
753  "T72x_LSC_READ_HITS",
754  "T72x_LSC_READ_MISSES",
755  "T72x_LSC_WRITE_HITS",
756  "T72x_LSC_WRITE_MISSES",
757  "T72x_LSC_ATOMIC_HITS",
758  "T72x_LSC_ATOMIC_MISSES",
759  "T72x_LSC_LINE_FETCHES",
760  "T72x_LSC_DIRTY_LINE",
761  "T72x_LSC_SNOOPS",
762  "",
763  "",
764  "",
765  "",
766  "",
767  "",
768  "",
769  "",
770  "",
771  "",
772  "",
773  "",
774  "",
775  "",
776  "",
777  "",
778  "",
779  "",
780  "",
781  "",
782  "",
783  "",
784  "",
785  "",
786  "",
787 
788  /*L2 and MMU */
789  "",
790  "",
791  "",
792  "",
793  "T72x_L2_EXT_WRITE_BEAT",
794  "T72x_L2_EXT_READ_BEAT",
795  "T72x_L2_READ_SNOOP",
796  "T72x_L2_READ_HIT",
797  "T72x_L2_WRITE_SNOOP",
798  "T72x_L2_WRITE_HIT",
799  "T72x_L2_EXT_WRITE_SMALL",
800  "T72x_L2_EXT_BARRIER",
801  "T72x_L2_EXT_AR_STALL",
802  "T72x_L2_EXT_W_STALL",
803  "T72x_L2_SNOOP_FULL",
804  "",
805  "",
806  "",
807  "",
808  "",
809  "",
810  "",
811  "",
812  "",
813  "",
814  "",
815  "",
816  "",
817  "",
818  "",
819  "",
820  "",
821  "",
822  "",
823  "",
824  "",
825  "",
826  "",
827  "",
828  "",
829  "",
830  "",
831  "",
832  "",
833  "",
834  "",
835  "",
836  "",
837  "",
838  "",
839  "",
840  "",
841  "",
842  "",
843  "",
844  "",
845  "",
846  "",
847  "",
848  "",
849  "",
850  "",
851  "",
852  ""
853 };
854 
855 static const char *const hardware_counters_mali_t76x[] =
856 {
857  /* Job Manager */
858  "",
859  "",
860  "",
861  "",
862  "T76x_MESSAGES_SENT",
863  "T76x_MESSAGES_RECEIVED",
864  "T76x_GPU_ACTIVE",
865  "T76x_IRQ_ACTIVE",
866  "T76x_JS0_JOBS",
867  "T76x_JS0_TASKS",
868  "T76x_JS0_ACTIVE",
869  "",
870  "T76x_JS0_WAIT_READ",
871  "T76x_JS0_WAIT_ISSUE",
872  "T76x_JS0_WAIT_DEPEND",
873  "T76x_JS0_WAIT_FINISH",
874  "T76x_JS1_JOBS",
875  "T76x_JS1_TASKS",
876  "T76x_JS1_ACTIVE",
877  "",
878  "T76x_JS1_WAIT_READ",
879  "T76x_JS1_WAIT_ISSUE",
880  "T76x_JS1_WAIT_DEPEND",
881  "T76x_JS1_WAIT_FINISH",
882  "T76x_JS2_JOBS",
883  "T76x_JS2_TASKS",
884  "T76x_JS2_ACTIVE",
885  "",
886  "T76x_JS2_WAIT_READ",
887  "T76x_JS2_WAIT_ISSUE",
888  "T76x_JS2_WAIT_DEPEND",
889  "T76x_JS2_WAIT_FINISH",
890  "",
891  "",
892  "",
893  "",
894  "",
895  "",
896  "",
897  "",
898  "",
899  "",
900  "",
901  "",
902  "",
903  "",
904  "",
905  "",
906  "",
907  "",
908  "",
909  "",
910  "",
911  "",
912  "",
913  "",
914  "",
915  "",
916  "",
917  "",
918  "",
919  "",
920  "",
921  "",
922 
923  /*Tiler */
924  "",
925  "",
926  "",
927  "T76x_TI_JOBS_PROCESSED",
928  "T76x_TI_TRIANGLES",
929  "T76x_TI_QUADS",
930  "T76x_TI_POLYGONS",
931  "T76x_TI_POINTS",
932  "T76x_TI_LINES",
933  "T76x_TI_VCACHE_HIT",
934  "T76x_TI_VCACHE_MISS",
935  "T76x_TI_FRONT_FACING",
936  "T76x_TI_BACK_FACING",
937  "T76x_TI_PRIM_VISIBLE",
938  "T76x_TI_PRIM_CULLED",
939  "T76x_TI_PRIM_CLIPPED",
940  "T76x_TI_LEVEL0",
941  "T76x_TI_LEVEL1",
942  "T76x_TI_LEVEL2",
943  "T76x_TI_LEVEL3",
944  "T76x_TI_LEVEL4",
945  "T76x_TI_LEVEL5",
946  "T76x_TI_LEVEL6",
947  "T76x_TI_LEVEL7",
948  "T76x_TI_COMMAND_1",
949  "T76x_TI_COMMAND_2",
950  "T76x_TI_COMMAND_3",
951  "T76x_TI_COMMAND_4",
952  "T76x_TI_COMMAND_5_7",
953  "T76x_TI_COMMAND_8_15",
954  "T76x_TI_COMMAND_16_63",
955  "T76x_TI_COMMAND_64",
956  "T76x_TI_COMPRESS_IN",
957  "T76x_TI_COMPRESS_OUT",
958  "T76x_TI_COMPRESS_FLUSH",
959  "T76x_TI_TIMESTAMPS",
960  "T76x_TI_PCACHE_HIT",
961  "T76x_TI_PCACHE_MISS",
962  "T76x_TI_PCACHE_LINE",
963  "T76x_TI_PCACHE_STALL",
964  "T76x_TI_WRBUF_HIT",
965  "T76x_TI_WRBUF_MISS",
966  "T76x_TI_WRBUF_LINE",
967  "T76x_TI_WRBUF_PARTIAL",
968  "T76x_TI_WRBUF_STALL",
969  "T76x_TI_ACTIVE",
970  "T76x_TI_LOADING_DESC",
971  "T76x_TI_INDEX_WAIT",
972  "T76x_TI_INDEX_RANGE_WAIT",
973  "T76x_TI_VERTEX_WAIT",
974  "T76x_TI_PCACHE_WAIT",
975  "T76x_TI_WRBUF_WAIT",
976  "T76x_TI_BUS_READ",
977  "T76x_TI_BUS_WRITE",
978  "",
979  "",
980  "",
981  "",
982  "",
983  "T76x_TI_UTLB_HIT",
984  "T76x_TI_UTLB_NEW_MISS",
985  "T76x_TI_UTLB_REPLAY_FULL",
986  "T76x_TI_UTLB_REPLAY_MISS",
987  "T76x_TI_UTLB_STALL",
988 
989  /* Shader Core */
990  "",
991  "",
992  "",
993  "",
994  "T76x_FRAG_ACTIVE",
995  "T76x_FRAG_PRIMITIVES",
996  "T76x_FRAG_PRIMITIVES_DROPPED",
997  "T76x_FRAG_CYCLES_DESC",
998  "T76x_FRAG_CYCLES_FPKQ_ACTIVE",
999  "T76x_FRAG_CYCLES_VERT",
1000  "T76x_FRAG_CYCLES_TRISETUP",
1001  "T76x_FRAG_CYCLES_EZS_ACTIVE",
1002  "T76x_FRAG_THREADS",
1003  "T76x_FRAG_DUMMY_THREADS",
1004  "T76x_FRAG_QUADS_RAST",
1005  "T76x_FRAG_QUADS_EZS_TEST",
1006  "T76x_FRAG_QUADS_EZS_KILLED",
1007  "T76x_FRAG_THREADS_LZS_TEST",
1008  "T76x_FRAG_THREADS_LZS_KILLED",
1009  "T76x_FRAG_CYCLES_NO_TILE",
1010  "T76x_FRAG_NUM_TILES",
1011  "T76x_FRAG_TRANS_ELIM",
1012  "T76x_COMPUTE_ACTIVE",
1013  "T76x_COMPUTE_TASKS",
1014  "T76x_COMPUTE_THREADS",
1015  "T76x_COMPUTE_CYCLES_DESC",
1016  "T76x_TRIPIPE_ACTIVE",
1017  "T76x_ARITH_WORDS",
1018  "T76x_ARITH_CYCLES_REG",
1019  "T76x_ARITH_CYCLES_L0",
1020  "T76x_ARITH_FRAG_DEPEND",
1021  "T76x_LS_WORDS",
1022  "T76x_LS_ISSUES",
1023  "T76x_LS_REISSUE_ATTR",
1024  "T76x_LS_REISSUES_VARY",
1025  "T76x_LS_VARY_RV_MISS",
1026  "T76x_LS_VARY_RV_HIT",
1027  "T76x_LS_NO_UNPARK",
1028  "T76x_TEX_WORDS",
1029  "T76x_TEX_BUBBLES",
1030  "T76x_TEX_WORDS_L0",
1031  "T76x_TEX_WORDS_DESC",
1032  "T76x_TEX_ISSUES",
1033  "T76x_TEX_RECIRC_FMISS",
1034  "T76x_TEX_RECIRC_DESC",
1035  "T76x_TEX_RECIRC_MULTI",
1036  "T76x_TEX_RECIRC_PMISS",
1037  "T76x_TEX_RECIRC_CONF",
1038  "T76x_LSC_READ_HITS",
1039  "T76x_LSC_READ_OP",
1040  "T76x_LSC_WRITE_HITS",
1041  "T76x_LSC_WRITE_OP",
1042  "T76x_LSC_ATOMIC_HITS",
1043  "T76x_LSC_ATOMIC_OP",
1044  "T76x_LSC_LINE_FETCHES",
1045  "T76x_LSC_DIRTY_LINE",
1046  "T76x_LSC_SNOOPS",
1047  "T76x_AXI_TLB_STALL",
1048  "T76x_AXI_TLB_MISS",
1049  "T76x_AXI_TLB_TRANSACTION",
1050  "T76x_LS_TLB_MISS",
1051  "T76x_LS_TLB_HIT",
1052  "T76x_AXI_BEATS_READ",
1053  "T76x_AXI_BEATS_WRITTEN",
1054 
1055  /*L2 and MMU */
1056  "",
1057  "",
1058  "",
1059  "",
1060  "T76x_MMU_HIT",
1061  "T76x_MMU_NEW_MISS",
1062  "T76x_MMU_REPLAY_FULL",
1063  "T76x_MMU_REPLAY_MISS",
1064  "T76x_MMU_TABLE_WALK",
1065  "T76x_MMU_REQUESTS",
1066  "",
1067  "",
1068  "T76x_UTLB_HIT",
1069  "T76x_UTLB_NEW_MISS",
1070  "T76x_UTLB_REPLAY_FULL",
1071  "T76x_UTLB_REPLAY_MISS",
1072  "T76x_UTLB_STALL",
1073  "",
1074  "",
1075  "",
1076  "",
1077  "",
1078  "",
1079  "",
1080  "",
1081  "",
1082  "",
1083  "",
1084  "",
1085  "",
1086  "T76x_L2_EXT_WRITE_BEATS",
1087  "T76x_L2_EXT_READ_BEATS",
1088  "T76x_L2_ANY_LOOKUP",
1089  "T76x_L2_READ_LOOKUP",
1090  "T76x_L2_SREAD_LOOKUP",
1091  "T76x_L2_READ_REPLAY",
1092  "T76x_L2_READ_SNOOP",
1093  "T76x_L2_READ_HIT",
1094  "T76x_L2_CLEAN_MISS",
1095  "T76x_L2_WRITE_LOOKUP",
1096  "T76x_L2_SWRITE_LOOKUP",
1097  "T76x_L2_WRITE_REPLAY",
1098  "T76x_L2_WRITE_SNOOP",
1099  "T76x_L2_WRITE_HIT",
1100  "T76x_L2_EXT_READ_FULL",
1101  "",
1102  "T76x_L2_EXT_WRITE_FULL",
1103  "T76x_L2_EXT_R_W_HAZARD",
1104  "T76x_L2_EXT_READ",
1105  "T76x_L2_EXT_READ_LINE",
1106  "T76x_L2_EXT_WRITE",
1107  "T76x_L2_EXT_WRITE_LINE",
1108  "T76x_L2_EXT_WRITE_SMALL",
1109  "T76x_L2_EXT_BARRIER",
1110  "T76x_L2_EXT_AR_STALL",
1111  "T76x_L2_EXT_R_BUF_FULL",
1112  "T76x_L2_EXT_RD_BUF_FULL",
1113  "T76x_L2_EXT_R_RAW",
1114  "T76x_L2_EXT_W_STALL",
1115  "T76x_L2_EXT_W_BUF_FULL",
1116  "T76x_L2_EXT_R_BUF_FULL",
1117  "T76x_L2_TAG_HAZARD",
1118  "T76x_L2_SNOOP_FULL",
1119  "T76x_L2_REPLAY_FULL"
1120 };
1121 
1122 static const char *const hardware_counters_mali_t82x[] =
1123 {
1124  /* Job Manager */
1125  "",
1126  "",
1127  "",
1128  "",
1129  "T82x_MESSAGES_SENT",
1130  "T82x_MESSAGES_RECEIVED",
1131  "T82x_GPU_ACTIVE",
1132  "T82x_IRQ_ACTIVE",
1133  "T82x_JS0_JOBS",
1134  "T82x_JS0_TASKS",
1135  "T82x_JS0_ACTIVE",
1136  "",
1137  "T82x_JS0_WAIT_READ",
1138  "T82x_JS0_WAIT_ISSUE",
1139  "T82x_JS0_WAIT_DEPEND",
1140  "T82x_JS0_WAIT_FINISH",
1141  "T82x_JS1_JOBS",
1142  "T82x_JS1_TASKS",
1143  "T82x_JS1_ACTIVE",
1144  "",
1145  "T82x_JS1_WAIT_READ",
1146  "T82x_JS1_WAIT_ISSUE",
1147  "T82x_JS1_WAIT_DEPEND",
1148  "T82x_JS1_WAIT_FINISH",
1149  "T82x_JS2_JOBS",
1150  "T82x_JS2_TASKS",
1151  "T82x_JS2_ACTIVE",
1152  "",
1153  "T82x_JS2_WAIT_READ",
1154  "T82x_JS2_WAIT_ISSUE",
1155  "T82x_JS2_WAIT_DEPEND",
1156  "T82x_JS2_WAIT_FINISH",
1157  "",
1158  "",
1159  "",
1160  "",
1161  "",
1162  "",
1163  "",
1164  "",
1165  "",
1166  "",
1167  "",
1168  "",
1169  "",
1170  "",
1171  "",
1172  "",
1173  "",
1174  "",
1175  "",
1176  "",
1177  "",
1178  "",
1179  "",
1180  "",
1181  "",
1182  "",
1183  "",
1184  "",
1185  "",
1186  "",
1187  "",
1188  "",
1189 
1190  /*Tiler */
1191  "",
1192  "",
1193  "",
1194  "T82x_TI_JOBS_PROCESSED",
1195  "T82x_TI_TRIANGLES",
1196  "T82x_TI_QUADS",
1197  "T82x_TI_POLYGONS",
1198  "T82x_TI_POINTS",
1199  "T82x_TI_LINES",
1200  "T82x_TI_FRONT_FACING",
1201  "T82x_TI_BACK_FACING",
1202  "T82x_TI_PRIM_VISIBLE",
1203  "T82x_TI_PRIM_CULLED",
1204  "T82x_TI_PRIM_CLIPPED",
1205  "",
1206  "",
1207  "",
1208  "",
1209  "",
1210  "",
1211  "",
1212  "",
1213  "T82x_TI_ACTIVE",
1214  "",
1215  "",
1216  "",
1217  "",
1218  "",
1219  "",
1220  "",
1221  "",
1222  "",
1223  "",
1224  "",
1225  "",
1226  "",
1227  "",
1228  "",
1229  "",
1230  "",
1231  "",
1232  "",
1233  "",
1234  "",
1235  "",
1236  "",
1237  "",
1238  "",
1239  "",
1240  "",
1241  "",
1242  "",
1243  "",
1244  "",
1245  "",
1246  "",
1247  "",
1248  "",
1249  "",
1250  "",
1251  "",
1252  "",
1253  "",
1254  "",
1255 
1256  /* Shader Core */
1257  "",
1258  "",
1259  "",
1260  "",
1261  "T82x_FRAG_ACTIVE",
1262  "T82x_FRAG_PRIMITIVES",
1263  "T82x_FRAG_PRIMITIVES_DROPPED",
1264  "T82x_FRAG_CYCLES_DESC",
1265  "T82x_FRAG_CYCLES_FPKQ_ACTIVE",
1266  "T82x_FRAG_CYCLES_VERT",
1267  "T82x_FRAG_CYCLES_TRISETUP",
1268  "T82x_FRAG_CYCLES_EZS_ACTIVE",
1269  "T82x_FRAG_THREADS",
1270  "T82x_FRAG_DUMMY_THREADS",
1271  "T82x_FRAG_QUADS_RAST",
1272  "T82x_FRAG_QUADS_EZS_TEST",
1273  "T82x_FRAG_QUADS_EZS_KILLED",
1274  "T82x_FRAG_THREADS_LZS_TEST",
1275  "T82x_FRAG_THREADS_LZS_KILLED",
1276  "T82x_FRAG_CYCLES_NO_TILE",
1277  "T82x_FRAG_NUM_TILES",
1278  "T82x_FRAG_TRANS_ELIM",
1279  "T82x_COMPUTE_ACTIVE",
1280  "T82x_COMPUTE_TASKS",
1281  "T82x_COMPUTE_THREADS",
1282  "T82x_COMPUTE_CYCLES_DESC",
1283  "T82x_TRIPIPE_ACTIVE",
1284  "T82x_ARITH_WORDS",
1285  "T82x_ARITH_CYCLES_REG",
1286  "T82x_ARITH_CYCLES_L0",
1287  "T82x_ARITH_FRAG_DEPEND",
1288  "T82x_LS_WORDS",
1289  "T82x_LS_ISSUES",
1290  "T82x_LS_REISSUE_ATTR",
1291  "T82x_LS_REISSUES_VARY",
1292  "T82x_LS_VARY_RV_MISS",
1293  "T82x_LS_VARY_RV_HIT",
1294  "T82x_LS_NO_UNPARK",
1295  "T82x_TEX_WORDS",
1296  "T82x_TEX_BUBBLES",
1297  "T82x_TEX_WORDS_L0",
1298  "T82x_TEX_WORDS_DESC",
1299  "T82x_TEX_ISSUES",
1300  "T82x_TEX_RECIRC_FMISS",
1301  "T82x_TEX_RECIRC_DESC",
1302  "T82x_TEX_RECIRC_MULTI",
1303  "T82x_TEX_RECIRC_PMISS",
1304  "T82x_TEX_RECIRC_CONF",
1305  "T82x_LSC_READ_HITS",
1306  "T82x_LSC_READ_OP",
1307  "T82x_LSC_WRITE_HITS",
1308  "T82x_LSC_WRITE_OP",
1309  "T82x_LSC_ATOMIC_HITS",
1310  "T82x_LSC_ATOMIC_OP",
1311  "T82x_LSC_LINE_FETCHES",
1312  "T82x_LSC_DIRTY_LINE",
1313  "T82x_LSC_SNOOPS",
1314  "T82x_AXI_TLB_STALL",
1315  "T82x_AXI_TLB_MISS",
1316  "T82x_AXI_TLB_TRANSACTION",
1317  "T82x_LS_TLB_MISS",
1318  "T82x_LS_TLB_HIT",
1319  "T82x_AXI_BEATS_READ",
1320  "T82x_AXI_BEATS_WRITTEN",
1321 
1322  /*L2 and MMU */
1323  "",
1324  "",
1325  "",
1326  "",
1327  "T82x_MMU_HIT",
1328  "T82x_MMU_NEW_MISS",
1329  "T82x_MMU_REPLAY_FULL",
1330  "T82x_MMU_REPLAY_MISS",
1331  "T82x_MMU_TABLE_WALK",
1332  "T82x_MMU_REQUESTS",
1333  "",
1334  "",
1335  "T82x_UTLB_HIT",
1336  "T82x_UTLB_NEW_MISS",
1337  "T82x_UTLB_REPLAY_FULL",
1338  "T82x_UTLB_REPLAY_MISS",
1339  "T82x_UTLB_STALL",
1340  "",
1341  "",
1342  "",
1343  "",
1344  "",
1345  "",
1346  "",
1347  "",
1348  "",
1349  "",
1350  "",
1351  "",
1352  "",
1353  "T82x_L2_EXT_WRITE_BEATS",
1354  "T82x_L2_EXT_READ_BEATS",
1355  "T82x_L2_ANY_LOOKUP",
1356  "T82x_L2_READ_LOOKUP",
1357  "T82x_L2_SREAD_LOOKUP",
1358  "T82x_L2_READ_REPLAY",
1359  "T82x_L2_READ_SNOOP",
1360  "T82x_L2_READ_HIT",
1361  "T82x_L2_CLEAN_MISS",
1362  "T82x_L2_WRITE_LOOKUP",
1363  "T82x_L2_SWRITE_LOOKUP",
1364  "T82x_L2_WRITE_REPLAY",
1365  "T82x_L2_WRITE_SNOOP",
1366  "T82x_L2_WRITE_HIT",
1367  "T82x_L2_EXT_READ_FULL",
1368  "",
1369  "T82x_L2_EXT_WRITE_FULL",
1370  "T82x_L2_EXT_R_W_HAZARD",
1371  "T82x_L2_EXT_READ",
1372  "T82x_L2_EXT_READ_LINE",
1373  "T82x_L2_EXT_WRITE",
1374  "T82x_L2_EXT_WRITE_LINE",
1375  "T82x_L2_EXT_WRITE_SMALL",
1376  "T82x_L2_EXT_BARRIER",
1377  "T82x_L2_EXT_AR_STALL",
1378  "T82x_L2_EXT_R_BUF_FULL",
1379  "T82x_L2_EXT_RD_BUF_FULL",
1380  "T82x_L2_EXT_R_RAW",
1381  "T82x_L2_EXT_W_STALL",
1382  "T82x_L2_EXT_W_BUF_FULL",
1383  "T82x_L2_EXT_R_BUF_FULL",
1384  "T82x_L2_TAG_HAZARD",
1385  "T82x_L2_SNOOP_FULL",
1386  "T82x_L2_REPLAY_FULL"
1387 };
1388 
1389 static const char *const hardware_counters_mali_t83x[] =
1390 {
1391  /* Job Manager */
1392  "",
1393  "",
1394  "",
1395  "",
1396  "T83x_MESSAGES_SENT",
1397  "T83x_MESSAGES_RECEIVED",
1398  "T83x_GPU_ACTIVE",
1399  "T83x_IRQ_ACTIVE",
1400  "T83x_JS0_JOBS",
1401  "T83x_JS0_TASKS",
1402  "T83x_JS0_ACTIVE",
1403  "",
1404  "T83x_JS0_WAIT_READ",
1405  "T83x_JS0_WAIT_ISSUE",
1406  "T83x_JS0_WAIT_DEPEND",
1407  "T83x_JS0_WAIT_FINISH",
1408  "T83x_JS1_JOBS",
1409  "T83x_JS1_TASKS",
1410  "T83x_JS1_ACTIVE",
1411  "",
1412  "T83x_JS1_WAIT_READ",
1413  "T83x_JS1_WAIT_ISSUE",
1414  "T83x_JS1_WAIT_DEPEND",
1415  "T83x_JS1_WAIT_FINISH",
1416  "T83x_JS2_JOBS",
1417  "T83x_JS2_TASKS",
1418  "T83x_JS2_ACTIVE",
1419  "",
1420  "T83x_JS2_WAIT_READ",
1421  "T83x_JS2_WAIT_ISSUE",
1422  "T83x_JS2_WAIT_DEPEND",
1423  "T83x_JS2_WAIT_FINISH",
1424  "",
1425  "",
1426  "",
1427  "",
1428  "",
1429  "",
1430  "",
1431  "",
1432  "",
1433  "",
1434  "",
1435  "",
1436  "",
1437  "",
1438  "",
1439  "",
1440  "",
1441  "",
1442  "",
1443  "",
1444  "",
1445  "",
1446  "",
1447  "",
1448  "",
1449  "",
1450  "",
1451  "",
1452  "",
1453  "",
1454  "",
1455  "",
1456 
1457  /*Tiler */
1458  "",
1459  "",
1460  "",
1461  "T83x_TI_JOBS_PROCESSED",
1462  "T83x_TI_TRIANGLES",
1463  "T83x_TI_QUADS",
1464  "T83x_TI_POLYGONS",
1465  "T83x_TI_POINTS",
1466  "T83x_TI_LINES",
1467  "T83x_TI_FRONT_FACING",
1468  "T83x_TI_BACK_FACING",
1469  "T83x_TI_PRIM_VISIBLE",
1470  "T83x_TI_PRIM_CULLED",
1471  "T83x_TI_PRIM_CLIPPED",
1472  "",
1473  "",
1474  "",
1475  "",
1476  "",
1477  "",
1478  "",
1479  "",
1480  "T83x_TI_ACTIVE",
1481  "",
1482  "",
1483  "",
1484  "",
1485  "",
1486  "",
1487  "",
1488  "",
1489  "",
1490  "",
1491  "",
1492  "",
1493  "",
1494  "",
1495  "",
1496  "",
1497  "",
1498  "",
1499  "",
1500  "",
1501  "",
1502  "",
1503  "",
1504  "",
1505  "",
1506  "",
1507  "",
1508  "",
1509  "",
1510  "",
1511  "",
1512  "",
1513  "",
1514  "",
1515  "",
1516  "",
1517  "",
1518  "",
1519  "",
1520  "",
1521  "",
1522 
1523  /* Shader Core */
1524  "",
1525  "",
1526  "",
1527  "",
1528  "T83x_FRAG_ACTIVE",
1529  "T83x_FRAG_PRIMITIVES",
1530  "T83x_FRAG_PRIMITIVES_DROPPED",
1531  "T83x_FRAG_CYCLES_DESC",
1532  "T83x_FRAG_CYCLES_FPKQ_ACTIVE",
1533  "T83x_FRAG_CYCLES_VERT",
1534  "T83x_FRAG_CYCLES_TRISETUP",
1535  "T83x_FRAG_CYCLES_EZS_ACTIVE",
1536  "T83x_FRAG_THREADS",
1537  "T83x_FRAG_DUMMY_THREADS",
1538  "T83x_FRAG_QUADS_RAST",
1539  "T83x_FRAG_QUADS_EZS_TEST",
1540  "T83x_FRAG_QUADS_EZS_KILLED",
1541  "T83x_FRAG_THREADS_LZS_TEST",
1542  "T83x_FRAG_THREADS_LZS_KILLED",
1543  "T83x_FRAG_CYCLES_NO_TILE",
1544  "T83x_FRAG_NUM_TILES",
1545  "T83x_FRAG_TRANS_ELIM",
1546  "T83x_COMPUTE_ACTIVE",
1547  "T83x_COMPUTE_TASKS",
1548  "T83x_COMPUTE_THREADS",
1549  "T83x_COMPUTE_CYCLES_DESC",
1550  "T83x_TRIPIPE_ACTIVE",
1551  "T83x_ARITH_WORDS",
1552  "T83x_ARITH_CYCLES_REG",
1553  "T83x_ARITH_CYCLES_L0",
1554  "T83x_ARITH_FRAG_DEPEND",
1555  "T83x_LS_WORDS",
1556  "T83x_LS_ISSUES",
1557  "T83x_LS_REISSUE_ATTR",
1558  "T83x_LS_REISSUES_VARY",
1559  "T83x_LS_VARY_RV_MISS",
1560  "T83x_LS_VARY_RV_HIT",
1561  "T83x_LS_NO_UNPARK",
1562  "T83x_TEX_WORDS",
1563  "T83x_TEX_BUBBLES",
1564  "T83x_TEX_WORDS_L0",
1565  "T83x_TEX_WORDS_DESC",
1566  "T83x_TEX_ISSUES",
1567  "T83x_TEX_RECIRC_FMISS",
1568  "T83x_TEX_RECIRC_DESC",
1569  "T83x_TEX_RECIRC_MULTI",
1570  "T83x_TEX_RECIRC_PMISS",
1571  "T83x_TEX_RECIRC_CONF",
1572  "T83x_LSC_READ_HITS",
1573  "T83x_LSC_READ_OP",
1574  "T83x_LSC_WRITE_HITS",
1575  "T83x_LSC_WRITE_OP",
1576  "T83x_LSC_ATOMIC_HITS",
1577  "T83x_LSC_ATOMIC_OP",
1578  "T83x_LSC_LINE_FETCHES",
1579  "T83x_LSC_DIRTY_LINE",
1580  "T83x_LSC_SNOOPS",
1581  "T83x_AXI_TLB_STALL",
1582  "T83x_AXI_TLB_MISS",
1583  "T83x_AXI_TLB_TRANSACTION",
1584  "T83x_LS_TLB_MISS",
1585  "T83x_LS_TLB_HIT",
1586  "T83x_AXI_BEATS_READ",
1587  "T83x_AXI_BEATS_WRITTEN",
1588 
1589  /*L2 and MMU */
1590  "",
1591  "",
1592  "",
1593  "",
1594  "T83x_MMU_HIT",
1595  "T83x_MMU_NEW_MISS",
1596  "T83x_MMU_REPLAY_FULL",
1597  "T83x_MMU_REPLAY_MISS",
1598  "T83x_MMU_TABLE_WALK",
1599  "T83x_MMU_REQUESTS",
1600  "",
1601  "",
1602  "T83x_UTLB_HIT",
1603  "T83x_UTLB_NEW_MISS",
1604  "T83x_UTLB_REPLAY_FULL",
1605  "T83x_UTLB_REPLAY_MISS",
1606  "T83x_UTLB_STALL",
1607  "",
1608  "",
1609  "",
1610  "",
1611  "",
1612  "",
1613  "",
1614  "",
1615  "",
1616  "",
1617  "",
1618  "",
1619  "",
1620  "T83x_L2_EXT_WRITE_BEATS",
1621  "T83x_L2_EXT_READ_BEATS",
1622  "T83x_L2_ANY_LOOKUP",
1623  "T83x_L2_READ_LOOKUP",
1624  "T83x_L2_SREAD_LOOKUP",
1625  "T83x_L2_READ_REPLAY",
1626  "T83x_L2_READ_SNOOP",
1627  "T83x_L2_READ_HIT",
1628  "T83x_L2_CLEAN_MISS",
1629  "T83x_L2_WRITE_LOOKUP",
1630  "T83x_L2_SWRITE_LOOKUP",
1631  "T83x_L2_WRITE_REPLAY",
1632  "T83x_L2_WRITE_SNOOP",
1633  "T83x_L2_WRITE_HIT",
1634  "T83x_L2_EXT_READ_FULL",
1635  "",
1636  "T83x_L2_EXT_WRITE_FULL",
1637  "T83x_L2_EXT_R_W_HAZARD",
1638  "T83x_L2_EXT_READ",
1639  "T83x_L2_EXT_READ_LINE",
1640  "T83x_L2_EXT_WRITE",
1641  "T83x_L2_EXT_WRITE_LINE",
1642  "T83x_L2_EXT_WRITE_SMALL",
1643  "T83x_L2_EXT_BARRIER",
1644  "T83x_L2_EXT_AR_STALL",
1645  "T83x_L2_EXT_R_BUF_FULL",
1646  "T83x_L2_EXT_RD_BUF_FULL",
1647  "T83x_L2_EXT_R_RAW",
1648  "T83x_L2_EXT_W_STALL",
1649  "T83x_L2_EXT_W_BUF_FULL",
1650  "T83x_L2_EXT_R_BUF_FULL",
1651  "T83x_L2_TAG_HAZARD",
1652  "T83x_L2_SNOOP_FULL",
1653  "T83x_L2_REPLAY_FULL"
1654 };
1655 
1656 static const char *const hardware_counters_mali_t86x[] =
1657 {
1658  /* Job Manager */
1659  "",
1660  "",
1661  "",
1662  "",
1663  "T86x_MESSAGES_SENT",
1664  "T86x_MESSAGES_RECEIVED",
1665  "T86x_GPU_ACTIVE",
1666  "T86x_IRQ_ACTIVE",
1667  "T86x_JS0_JOBS",
1668  "T86x_JS0_TASKS",
1669  "T86x_JS0_ACTIVE",
1670  "",
1671  "T86x_JS0_WAIT_READ",
1672  "T86x_JS0_WAIT_ISSUE",
1673  "T86x_JS0_WAIT_DEPEND",
1674  "T86x_JS0_WAIT_FINISH",
1675  "T86x_JS1_JOBS",
1676  "T86x_JS1_TASKS",
1677  "T86x_JS1_ACTIVE",
1678  "",
1679  "T86x_JS1_WAIT_READ",
1680  "T86x_JS1_WAIT_ISSUE",
1681  "T86x_JS1_WAIT_DEPEND",
1682  "T86x_JS1_WAIT_FINISH",
1683  "T86x_JS2_JOBS",
1684  "T86x_JS2_TASKS",
1685  "T86x_JS2_ACTIVE",
1686  "",
1687  "T86x_JS2_WAIT_READ",
1688  "T86x_JS2_WAIT_ISSUE",
1689  "T86x_JS2_WAIT_DEPEND",
1690  "T86x_JS2_WAIT_FINISH",
1691  "",
1692  "",
1693  "",
1694  "",
1695  "",
1696  "",
1697  "",
1698  "",
1699  "",
1700  "",
1701  "",
1702  "",
1703  "",
1704  "",
1705  "",
1706  "",
1707  "",
1708  "",
1709  "",
1710  "",
1711  "",
1712  "",
1713  "",
1714  "",
1715  "",
1716  "",
1717  "",
1718  "",
1719  "",
1720  "",
1721  "",
1722  "",
1723 
1724  /*Tiler */
1725  "",
1726  "",
1727  "",
1728  "T86x_TI_JOBS_PROCESSED",
1729  "T86x_TI_TRIANGLES",
1730  "T86x_TI_QUADS",
1731  "T86x_TI_POLYGONS",
1732  "T86x_TI_POINTS",
1733  "T86x_TI_LINES",
1734  "T86x_TI_VCACHE_HIT",
1735  "T86x_TI_VCACHE_MISS",
1736  "T86x_TI_FRONT_FACING",
1737  "T86x_TI_BACK_FACING",
1738  "T86x_TI_PRIM_VISIBLE",
1739  "T86x_TI_PRIM_CULLED",
1740  "T86x_TI_PRIM_CLIPPED",
1741  "T86x_TI_LEVEL0",
1742  "T86x_TI_LEVEL1",
1743  "T86x_TI_LEVEL2",
1744  "T86x_TI_LEVEL3",
1745  "T86x_TI_LEVEL4",
1746  "T86x_TI_LEVEL5",
1747  "T86x_TI_LEVEL6",
1748  "T86x_TI_LEVEL7",
1749  "T86x_TI_COMMAND_1",
1750  "T86x_TI_COMMAND_2",
1751  "T86x_TI_COMMAND_3",
1752  "T86x_TI_COMMAND_4",
1753  "T86x_TI_COMMAND_5_7",
1754  "T86x_TI_COMMAND_8_15",
1755  "T86x_TI_COMMAND_16_63",
1756  "T86x_TI_COMMAND_64",
1757  "T86x_TI_COMPRESS_IN",
1758  "T86x_TI_COMPRESS_OUT",
1759  "T86x_TI_COMPRESS_FLUSH",
1760  "T86x_TI_TIMESTAMPS",
1761  "T86x_TI_PCACHE_HIT",
1762  "T86x_TI_PCACHE_MISS",
1763  "T86x_TI_PCACHE_LINE",
1764  "T86x_TI_PCACHE_STALL",
1765  "T86x_TI_WRBUF_HIT",
1766  "T86x_TI_WRBUF_MISS",
1767  "T86x_TI_WRBUF_LINE",
1768  "T86x_TI_WRBUF_PARTIAL",
1769  "T86x_TI_WRBUF_STALL",
1770  "T86x_TI_ACTIVE",
1771  "T86x_TI_LOADING_DESC",
1772  "T86x_TI_INDEX_WAIT",
1773  "T86x_TI_INDEX_RANGE_WAIT",
1774  "T86x_TI_VERTEX_WAIT",
1775  "T86x_TI_PCACHE_WAIT",
1776  "T86x_TI_WRBUF_WAIT",
1777  "T86x_TI_BUS_READ",
1778  "T86x_TI_BUS_WRITE",
1779  "",
1780  "",
1781  "",
1782  "",
1783  "",
1784  "T86x_TI_UTLB_HIT",
1785  "T86x_TI_UTLB_NEW_MISS",
1786  "T86x_TI_UTLB_REPLAY_FULL",
1787  "T86x_TI_UTLB_REPLAY_MISS",
1788  "T86x_TI_UTLB_STALL",
1789 
1790  /* Shader Core */
1791  "",
1792  "",
1793  "",
1794  "",
1795  "T86x_FRAG_ACTIVE",
1796  "T86x_FRAG_PRIMITIVES",
1797  "T86x_FRAG_PRIMITIVES_DROPPED",
1798  "T86x_FRAG_CYCLES_DESC",
1799  "T86x_FRAG_CYCLES_FPKQ_ACTIVE",
1800  "T86x_FRAG_CYCLES_VERT",
1801  "T86x_FRAG_CYCLES_TRISETUP",
1802  "T86x_FRAG_CYCLES_EZS_ACTIVE",
1803  "T86x_FRAG_THREADS",
1804  "T86x_FRAG_DUMMY_THREADS",
1805  "T86x_FRAG_QUADS_RAST",
1806  "T86x_FRAG_QUADS_EZS_TEST",
1807  "T86x_FRAG_QUADS_EZS_KILLED",
1808  "T86x_FRAG_THREADS_LZS_TEST",
1809  "T86x_FRAG_THREADS_LZS_KILLED",
1810  "T86x_FRAG_CYCLES_NO_TILE",
1811  "T86x_FRAG_NUM_TILES",
1812  "T86x_FRAG_TRANS_ELIM",
1813  "T86x_COMPUTE_ACTIVE",
1814  "T86x_COMPUTE_TASKS",
1815  "T86x_COMPUTE_THREADS",
1816  "T86x_COMPUTE_CYCLES_DESC",
1817  "T86x_TRIPIPE_ACTIVE",
1818  "T86x_ARITH_WORDS",
1819  "T86x_ARITH_CYCLES_REG",
1820  "T86x_ARITH_CYCLES_L0",
1821  "T86x_ARITH_FRAG_DEPEND",
1822  "T86x_LS_WORDS",
1823  "T86x_LS_ISSUES",
1824  "T86x_LS_REISSUE_ATTR",
1825  "T86x_LS_REISSUES_VARY",
1826  "T86x_LS_VARY_RV_MISS",
1827  "T86x_LS_VARY_RV_HIT",
1828  "T86x_LS_NO_UNPARK",
1829  "T86x_TEX_WORDS",
1830  "T86x_TEX_BUBBLES",
1831  "T86x_TEX_WORDS_L0",
1832  "T86x_TEX_WORDS_DESC",
1833  "T86x_TEX_ISSUES",
1834  "T86x_TEX_RECIRC_FMISS",
1835  "T86x_TEX_RECIRC_DESC",
1836  "T86x_TEX_RECIRC_MULTI",
1837  "T86x_TEX_RECIRC_PMISS",
1838  "T86x_TEX_RECIRC_CONF",
1839  "T86x_LSC_READ_HITS",
1840  "T86x_LSC_READ_OP",
1841  "T86x_LSC_WRITE_HITS",
1842  "T86x_LSC_WRITE_OP",
1843  "T86x_LSC_ATOMIC_HITS",
1844  "T86x_LSC_ATOMIC_OP",
1845  "T86x_LSC_LINE_FETCHES",
1846  "T86x_LSC_DIRTY_LINE",
1847  "T86x_LSC_SNOOPS",
1848  "T86x_AXI_TLB_STALL",
1849  "T86x_AXI_TLB_MISS",
1850  "T86x_AXI_TLB_TRANSACTION",
1851  "T86x_LS_TLB_MISS",
1852  "T86x_LS_TLB_HIT",
1853  "T86x_AXI_BEATS_READ",
1854  "T86x_AXI_BEATS_WRITTEN",
1855 
1856  /*L2 and MMU */
1857  "",
1858  "",
1859  "",
1860  "",
1861  "T86x_MMU_HIT",
1862  "T86x_MMU_NEW_MISS",
1863  "T86x_MMU_REPLAY_FULL",
1864  "T86x_MMU_REPLAY_MISS",
1865  "T86x_MMU_TABLE_WALK",
1866  "T86x_MMU_REQUESTS",
1867  "",
1868  "",
1869  "T86x_UTLB_HIT",
1870  "T86x_UTLB_NEW_MISS",
1871  "T86x_UTLB_REPLAY_FULL",
1872  "T86x_UTLB_REPLAY_MISS",
1873  "T86x_UTLB_STALL",
1874  "",
1875  "",
1876  "",
1877  "",
1878  "",
1879  "",
1880  "",
1881  "",
1882  "",
1883  "",
1884  "",
1885  "",
1886  "",
1887  "T86x_L2_EXT_WRITE_BEATS",
1888  "T86x_L2_EXT_READ_BEATS",
1889  "T86x_L2_ANY_LOOKUP",
1890  "T86x_L2_READ_LOOKUP",
1891  "T86x_L2_SREAD_LOOKUP",
1892  "T86x_L2_READ_REPLAY",
1893  "T86x_L2_READ_SNOOP",
1894  "T86x_L2_READ_HIT",
1895  "T86x_L2_CLEAN_MISS",
1896  "T86x_L2_WRITE_LOOKUP",
1897  "T86x_L2_SWRITE_LOOKUP",
1898  "T86x_L2_WRITE_REPLAY",
1899  "T86x_L2_WRITE_SNOOP",
1900  "T86x_L2_WRITE_HIT",
1901  "T86x_L2_EXT_READ_FULL",
1902  "",
1903  "T86x_L2_EXT_WRITE_FULL",
1904  "T86x_L2_EXT_R_W_HAZARD",
1905  "T86x_L2_EXT_READ",
1906  "T86x_L2_EXT_READ_LINE",
1907  "T86x_L2_EXT_WRITE",
1908  "T86x_L2_EXT_WRITE_LINE",
1909  "T86x_L2_EXT_WRITE_SMALL",
1910  "T86x_L2_EXT_BARRIER",
1911  "T86x_L2_EXT_AR_STALL",
1912  "T86x_L2_EXT_R_BUF_FULL",
1913  "T86x_L2_EXT_RD_BUF_FULL",
1914  "T86x_L2_EXT_R_RAW",
1915  "T86x_L2_EXT_W_STALL",
1916  "T86x_L2_EXT_W_BUF_FULL",
1917  "T86x_L2_EXT_R_BUF_FULL",
1918  "T86x_L2_TAG_HAZARD",
1919  "T86x_L2_SNOOP_FULL",
1920  "T86x_L2_REPLAY_FULL"
1921 };
1922 
1923 static const char *const hardware_counters_mali_t88x[] =
1924 {
1925  /* Job Manager */
1926  "",
1927  "",
1928  "",
1929  "",
1930  "T88x_MESSAGES_SENT",
1931  "T88x_MESSAGES_RECEIVED",
1932  "T88x_GPU_ACTIVE",
1933  "T88x_IRQ_ACTIVE",
1934  "T88x_JS0_JOBS",
1935  "T88x_JS0_TASKS",
1936  "T88x_JS0_ACTIVE",
1937  "",
1938  "T88x_JS0_WAIT_READ",
1939  "T88x_JS0_WAIT_ISSUE",
1940  "T88x_JS0_WAIT_DEPEND",
1941  "T88x_JS0_WAIT_FINISH",
1942  "T88x_JS1_JOBS",
1943  "T88x_JS1_TASKS",
1944  "T88x_JS1_ACTIVE",
1945  "",
1946  "T88x_JS1_WAIT_READ",
1947  "T88x_JS1_WAIT_ISSUE",
1948  "T88x_JS1_WAIT_DEPEND",
1949  "T88x_JS1_WAIT_FINISH",
1950  "T88x_JS2_JOBS",
1951  "T88x_JS2_TASKS",
1952  "T88x_JS2_ACTIVE",
1953  "",
1954  "T88x_JS2_WAIT_READ",
1955  "T88x_JS2_WAIT_ISSUE",
1956  "T88x_JS2_WAIT_DEPEND",
1957  "T88x_JS2_WAIT_FINISH",
1958  "",
1959  "",
1960  "",
1961  "",
1962  "",
1963  "",
1964  "",
1965  "",
1966  "",
1967  "",
1968  "",
1969  "",
1970  "",
1971  "",
1972  "",
1973  "",
1974  "",
1975  "",
1976  "",
1977  "",
1978  "",
1979  "",
1980  "",
1981  "",
1982  "",
1983  "",
1984  "",
1985  "",
1986  "",
1987  "",
1988  "",
1989  "",
1990 
1991  /*Tiler */
1992  "",
1993  "",
1994  "",
1995  "T88x_TI_JOBS_PROCESSED",
1996  "T88x_TI_TRIANGLES",
1997  "T88x_TI_QUADS",
1998  "T88x_TI_POLYGONS",
1999  "T88x_TI_POINTS",
2000  "T88x_TI_LINES",
2001  "T88x_TI_VCACHE_HIT",
2002  "T88x_TI_VCACHE_MISS",
2003  "T88x_TI_FRONT_FACING",
2004  "T88x_TI_BACK_FACING",
2005  "T88x_TI_PRIM_VISIBLE",
2006  "T88x_TI_PRIM_CULLED",
2007  "T88x_TI_PRIM_CLIPPED",
2008  "T88x_TI_LEVEL0",
2009  "T88x_TI_LEVEL1",
2010  "T88x_TI_LEVEL2",
2011  "T88x_TI_LEVEL3",
2012  "T88x_TI_LEVEL4",
2013  "T88x_TI_LEVEL5",
2014  "T88x_TI_LEVEL6",
2015  "T88x_TI_LEVEL7",
2016  "T88x_TI_COMMAND_1",
2017  "T88x_TI_COMMAND_2",
2018  "T88x_TI_COMMAND_3",
2019  "T88x_TI_COMMAND_4",
2020  "T88x_TI_COMMAND_5_7",
2021  "T88x_TI_COMMAND_8_15",
2022  "T88x_TI_COMMAND_16_63",
2023  "T88x_TI_COMMAND_64",
2024  "T88x_TI_COMPRESS_IN",
2025  "T88x_TI_COMPRESS_OUT",
2026  "T88x_TI_COMPRESS_FLUSH",
2027  "T88x_TI_TIMESTAMPS",
2028  "T88x_TI_PCACHE_HIT",
2029  "T88x_TI_PCACHE_MISS",
2030  "T88x_TI_PCACHE_LINE",
2031  "T88x_TI_PCACHE_STALL",
2032  "T88x_TI_WRBUF_HIT",
2033  "T88x_TI_WRBUF_MISS",
2034  "T88x_TI_WRBUF_LINE",
2035  "T88x_TI_WRBUF_PARTIAL",
2036  "T88x_TI_WRBUF_STALL",
2037  "T88x_TI_ACTIVE",
2038  "T88x_TI_LOADING_DESC",
2039  "T88x_TI_INDEX_WAIT",
2040  "T88x_TI_INDEX_RANGE_WAIT",
2041  "T88x_TI_VERTEX_WAIT",
2042  "T88x_TI_PCACHE_WAIT",
2043  "T88x_TI_WRBUF_WAIT",
2044  "T88x_TI_BUS_READ",
2045  "T88x_TI_BUS_WRITE",
2046  "",
2047  "",
2048  "",
2049  "",
2050  "",
2051  "T88x_TI_UTLB_HIT",
2052  "T88x_TI_UTLB_NEW_MISS",
2053  "T88x_TI_UTLB_REPLAY_FULL",
2054  "T88x_TI_UTLB_REPLAY_MISS",
2055  "T88x_TI_UTLB_STALL",
2056 
2057  /* Shader Core */
2058  "",
2059  "",
2060  "",
2061  "",
2062  "T88x_FRAG_ACTIVE",
2063  "T88x_FRAG_PRIMITIVES",
2064  "T88x_FRAG_PRIMITIVES_DROPPED",
2065  "T88x_FRAG_CYCLES_DESC",
2066  "T88x_FRAG_CYCLES_FPKQ_ACTIVE",
2067  "T88x_FRAG_CYCLES_VERT",
2068  "T88x_FRAG_CYCLES_TRISETUP",
2069  "T88x_FRAG_CYCLES_EZS_ACTIVE",
2070  "T88x_FRAG_THREADS",
2071  "T88x_FRAG_DUMMY_THREADS",
2072  "T88x_FRAG_QUADS_RAST",
2073  "T88x_FRAG_QUADS_EZS_TEST",
2074  "T88x_FRAG_QUADS_EZS_KILLED",
2075  "T88x_FRAG_THREADS_LZS_TEST",
2076  "T88x_FRAG_THREADS_LZS_KILLED",
2077  "T88x_FRAG_CYCLES_NO_TILE",
2078  "T88x_FRAG_NUM_TILES",
2079  "T88x_FRAG_TRANS_ELIM",
2080  "T88x_COMPUTE_ACTIVE",
2081  "T88x_COMPUTE_TASKS",
2082  "T88x_COMPUTE_THREADS",
2083  "T88x_COMPUTE_CYCLES_DESC",
2084  "T88x_TRIPIPE_ACTIVE",
2085  "T88x_ARITH_WORDS",
2086  "T88x_ARITH_CYCLES_REG",
2087  "T88x_ARITH_CYCLES_L0",
2088  "T88x_ARITH_FRAG_DEPEND",
2089  "T88x_LS_WORDS",
2090  "T88x_LS_ISSUES",
2091  "T88x_LS_REISSUE_ATTR",
2092  "T88x_LS_REISSUES_VARY",
2093  "T88x_LS_VARY_RV_MISS",
2094  "T88x_LS_VARY_RV_HIT",
2095  "T88x_LS_NO_UNPARK",
2096  "T88x_TEX_WORDS",
2097  "T88x_TEX_BUBBLES",
2098  "T88x_TEX_WORDS_L0",
2099  "T88x_TEX_WORDS_DESC",
2100  "T88x_TEX_ISSUES",
2101  "T88x_TEX_RECIRC_FMISS",
2102  "T88x_TEX_RECIRC_DESC",
2103  "T88x_TEX_RECIRC_MULTI",
2104  "T88x_TEX_RECIRC_PMISS",
2105  "T88x_TEX_RECIRC_CONF",
2106  "T88x_LSC_READ_HITS",
2107  "T88x_LSC_READ_OP",
2108  "T88x_LSC_WRITE_HITS",
2109  "T88x_LSC_WRITE_OP",
2110  "T88x_LSC_ATOMIC_HITS",
2111  "T88x_LSC_ATOMIC_OP",
2112  "T88x_LSC_LINE_FETCHES",
2113  "T88x_LSC_DIRTY_LINE",
2114  "T88x_LSC_SNOOPS",
2115  "T88x_AXI_TLB_STALL",
2116  "T88x_AXI_TLB_MISS",
2117  "T88x_AXI_TLB_TRANSACTION",
2118  "T88x_LS_TLB_MISS",
2119  "T88x_LS_TLB_HIT",
2120  "T88x_AXI_BEATS_READ",
2121  "T88x_AXI_BEATS_WRITTEN",
2122 
2123  /*L2 and MMU */
2124  "",
2125  "",
2126  "",
2127  "",
2128  "T88x_MMU_HIT",
2129  "T88x_MMU_NEW_MISS",
2130  "T88x_MMU_REPLAY_FULL",
2131  "T88x_MMU_REPLAY_MISS",
2132  "T88x_MMU_TABLE_WALK",
2133  "T88x_MMU_REQUESTS",
2134  "",
2135  "",
2136  "T88x_UTLB_HIT",
2137  "T88x_UTLB_NEW_MISS",
2138  "T88x_UTLB_REPLAY_FULL",
2139  "T88x_UTLB_REPLAY_MISS",
2140  "T88x_UTLB_STALL",
2141  "",
2142  "",
2143  "",
2144  "",
2145  "",
2146  "",
2147  "",
2148  "",
2149  "",
2150  "",
2151  "",
2152  "",
2153  "",
2154  "T88x_L2_EXT_WRITE_BEATS",
2155  "T88x_L2_EXT_READ_BEATS",
2156  "T88x_L2_ANY_LOOKUP",
2157  "T88x_L2_READ_LOOKUP",
2158  "T88x_L2_SREAD_LOOKUP",
2159  "T88x_L2_READ_REPLAY",
2160  "T88x_L2_READ_SNOOP",
2161  "T88x_L2_READ_HIT",
2162  "T88x_L2_CLEAN_MISS",
2163  "T88x_L2_WRITE_LOOKUP",
2164  "T88x_L2_SWRITE_LOOKUP",
2165  "T88x_L2_WRITE_REPLAY",
2166  "T88x_L2_WRITE_SNOOP",
2167  "T88x_L2_WRITE_HIT",
2168  "T88x_L2_EXT_READ_FULL",
2169  "",
2170  "T88x_L2_EXT_WRITE_FULL",
2171  "T88x_L2_EXT_R_W_HAZARD",
2172  "T88x_L2_EXT_READ",
2173  "T88x_L2_EXT_READ_LINE",
2174  "T88x_L2_EXT_WRITE",
2175  "T88x_L2_EXT_WRITE_LINE",
2176  "T88x_L2_EXT_WRITE_SMALL",
2177  "T88x_L2_EXT_BARRIER",
2178  "T88x_L2_EXT_AR_STALL",
2179  "T88x_L2_EXT_R_BUF_FULL",
2180  "T88x_L2_EXT_RD_BUF_FULL",
2181  "T88x_L2_EXT_R_RAW",
2182  "T88x_L2_EXT_W_STALL",
2183  "T88x_L2_EXT_W_BUF_FULL",
2184  "T88x_L2_EXT_R_BUF_FULL",
2185  "T88x_L2_TAG_HAZARD",
2186  "T88x_L2_SNOOP_FULL",
2187  "T88x_L2_REPLAY_FULL"
2188 };
2189 
2190 static const char *const hardware_counters_mali_tHEx[] =
2191 {
2192  /* Performance counters for the Job Manager */
2193  "",
2194  "",
2195  "",
2196  "",
2197  "THEx_MESSAGES_SENT",
2198  "THEx_MESSAGES_RECEIVED",
2199  "THEx_GPU_ACTIVE",
2200  "THEx_IRQ_ACTIVE",
2201  "THEx_JS0_JOBS",
2202  "THEx_JS0_TASKS",
2203  "THEx_JS0_ACTIVE",
2204  "",
2205  "THEx_JS0_WAIT_READ",
2206  "THEx_JS0_WAIT_ISSUE",
2207  "THEx_JS0_WAIT_DEPEND",
2208  "THEx_JS0_WAIT_FINISH",
2209  "THEx_JS1_JOBS",
2210  "THEx_JS1_TASKS",
2211  "THEx_JS1_ACTIVE",
2212  "",
2213  "THEx_JS1_WAIT_READ",
2214  "THEx_JS1_WAIT_ISSUE",
2215  "THEx_JS1_WAIT_DEPEND",
2216  "THEx_JS1_WAIT_FINISH",
2217  "THEx_JS2_JOBS",
2218  "THEx_JS2_TASKS",
2219  "THEx_JS2_ACTIVE",
2220  "",
2221  "THEx_JS2_WAIT_READ",
2222  "THEx_JS2_WAIT_ISSUE",
2223  "THEx_JS2_WAIT_DEPEND",
2224  "THEx_JS2_WAIT_FINISH",
2225  "",
2226  "",
2227  "",
2228  "",
2229  "",
2230  "",
2231  "",
2232  "",
2233  "",
2234  "",
2235  "",
2236  "",
2237  "",
2238  "",
2239  "",
2240  "",
2241  "",
2242  "",
2243  "",
2244  "",
2245  "",
2246  "",
2247  "",
2248  "",
2249  "",
2250  "",
2251  "",
2252  "",
2253  "",
2254  "",
2255  "",
2256  "",
2257 
2258  /* Performance counters for the Tiler */
2259  "",
2260  "",
2261  "",
2262  "",
2263  "THEx_TILER_ACTIVE",
2264  "THEx_JOBS_PROCESSED",
2265  "THEx_TRIANGLES",
2266  "THEx_LINES",
2267  "THEx_POINTS",
2268  "THEx_FRONT_FACING",
2269  "THEx_BACK_FACING",
2270  "THEx_PRIM_VISIBLE",
2271  "THEx_PRIM_CULLED",
2272  "THEx_PRIM_CLIPPED",
2273  "THEx_PRIM_SAT_CULLED",
2274  "",
2275  "",
2276  "THEx_BUS_READ",
2277  "",
2278  "THEx_BUS_WRITE",
2279  "THEx_LOADING_DESC",
2280  "THEx_IDVS_POS_SHAD_REQ",
2281  "THEx_IDVS_POS_SHAD_WAIT",
2282  "THEx_IDVS_POS_SHAD_STALL",
2283  "THEx_IDVS_POS_FIFO_FULL",
2284  "THEx_PREFETCH_STALL",
2285  "THEx_VCACHE_HIT",
2286  "THEx_VCACHE_MISS",
2287  "THEx_VCACHE_LINE_WAIT",
2288  "THEx_VFETCH_POS_READ_WAIT",
2289  "THEx_VFETCH_VERTEX_WAIT",
2290  "THEx_VFETCH_STALL",
2291  "THEx_PRIMASSY_STALL",
2292  "THEx_BBOX_GEN_STALL",
2293  "THEx_IDVS_VBU_HIT",
2294  "THEx_IDVS_VBU_MISS",
2295  "THEx_IDVS_VBU_LINE_DEALLOCATE",
2296  "THEx_IDVS_VAR_SHAD_REQ",
2297  "THEx_IDVS_VAR_SHAD_STALL",
2298  "THEx_BINNER_STALL",
2299  "THEx_ITER_STALL",
2300  "THEx_COMPRESS_MISS",
2301  "THEx_COMPRESS_STALL",
2302  "THEx_PCACHE_HIT",
2303  "THEx_PCACHE_MISS",
2304  "THEx_PCACHE_MISS_STALL",
2305  "THEx_PCACHE_EVICT_STALL",
2306  "THEx_PMGR_PTR_WR_STALL",
2307  "THEx_PMGR_PTR_RD_STALL",
2308  "THEx_PMGR_CMD_WR_STALL",
2309  "THEx_WRBUF_ACTIVE",
2310  "THEx_WRBUF_HIT",
2311  "THEx_WRBUF_MISS",
2312  "THEx_WRBUF_NO_FREE_LINE_STALL",
2313  "THEx_WRBUF_NO_AXI_ID_STALL",
2314  "THEx_WRBUF_AXI_STALL",
2315  "",
2316  "",
2317  "",
2318  "THEx_UTLB_TRANS",
2319  "THEx_UTLB_TRANS_HIT",
2320  "THEx_UTLB_TRANS_STALL",
2321  "THEx_UTLB_TRANS_MISS_DELAY",
2322  "THEx_UTLB_MMU_REQ",
2323 
2324  /* Performance counters for the Shader Core */
2325  "",
2326  "",
2327  "",
2328  "",
2329  "THEx_FRAG_ACTIVE",
2330  "THEx_FRAG_PRIMITIVES",
2331  "THEx_FRAG_PRIM_RAST",
2332  "THEx_FRAG_FPK_ACTIVE",
2333  "THEx_FRAG_STARVING",
2334  "THEx_FRAG_WARPS",
2335  "THEx_FRAG_PARTIAL_WARPS",
2336  "THEx_FRAG_QUADS_RAST",
2337  "THEx_FRAG_QUADS_EZS_TEST",
2338  "THEx_FRAG_QUADS_EZS_UPDATE",
2339  "THEx_FRAG_QUADS_EZS_KILL",
2340  "THEx_FRAG_LZS_TEST",
2341  "THEx_FRAG_LZS_KILL",
2342  "",
2343  "THEx_FRAG_PTILES",
2344  "THEx_FRAG_TRANS_ELIM",
2345  "THEx_QUAD_FPK_KILLER",
2346  "",
2347  "THEx_COMPUTE_ACTIVE",
2348  "THEx_COMPUTE_TASKS",
2349  "THEx_COMPUTE_WARPS",
2350  "THEx_COMPUTE_STARVING",
2351  "THEx_EXEC_CORE_ACTIVE",
2352  "THEx_EXEC_ACTIVE",
2353  "THEx_EXEC_INSTR_COUNT",
2354  "THEx_EXEC_INSTR_DIVERGED",
2355  "THEx_EXEC_INSTR_STARVING",
2356  "THEx_ARITH_INSTR_SINGLE_FMA",
2357  "THEx_ARITH_INSTR_DOUBLE",
2358  "THEx_ARITH_INSTR_MSG",
2359  "THEx_ARITH_INSTR_MSG_ONLY",
2360  "THEx_TEX_INSTR",
2361  "THEx_TEX_INSTR_MIPMAP",
2362  "THEx_TEX_INSTR_COMPRESSED",
2363  "THEx_TEX_INSTR_3D",
2364  "THEx_TEX_INSTR_TRILINEAR",
2365  "THEx_TEX_COORD_ISSUE",
2366  "THEx_TEX_COORD_STALL",
2367  "THEx_TEX_STARVE_CACHE",
2368  "THEx_TEX_STARVE_FILTER",
2369  "THEx_LS_MEM_READ_FULL",
2370  "THEx_LS_MEM_READ_SHORT",
2371  "THEx_LS_MEM_WRITE_FULL",
2372  "THEx_LS_MEM_WRITE_SHORT",
2373  "THEx_LS_MEM_ATOMIC",
2374  "THEx_VARY_INSTR",
2375  "THEx_VARY_SLOT_32",
2376  "THEx_VARY_SLOT_16",
2377  "THEx_ATTR_INSTR",
2378  "THEx_ARITH_INSTR_FP_MUL",
2379  "THEx_BEATS_RD_FTC",
2380  "THEx_BEATS_RD_FTC_EXT",
2381  "THEx_BEATS_RD_LSC",
2382  "THEx_BEATS_RD_LSC_EXT",
2383  "THEx_BEATS_RD_TEX",
2384  "THEx_BEATS_RD_TEX_EXT",
2385  "THEx_BEATS_RD_OTHER",
2386  "THEx_BEATS_WR_LSC",
2387  "THEx_BEATS_WR_TIB",
2388  "",
2389 
2390  /* Performance counters for the Memory System */
2391  "",
2392  "",
2393  "",
2394  "",
2395  "THEx_MMU_REQUESTS",
2396  "",
2397  "",
2398  "",
2399  "",
2400  "",
2401  "",
2402  "",
2403  "",
2404  "",
2405  "",
2406  "",
2407  "THEx_L2_RD_MSG_IN",
2408  "THEx_L2_RD_MSG_IN_STALL",
2409  "THEx_L2_WR_MSG_IN",
2410  "THEx_L2_WR_MSG_IN_STALL",
2411  "THEx_L2_SNP_MSG_IN",
2412  "THEx_L2_SNP_MSG_IN_STALL",
2413  "THEx_L2_RD_MSG_OUT",
2414  "THEx_L2_RD_MSG_OUT_STALL",
2415  "THEx_L2_WR_MSG_OUT",
2416  "THEx_L2_ANY_LOOKUP",
2417  "THEx_L2_READ_LOOKUP",
2418  "THEx_L2_WRITE_LOOKUP",
2419  "THEx_L2_EXT_SNOOP_LOOKUP",
2420  "THEx_L2_EXT_READ",
2421  "THEx_L2_EXT_READ_NOSNP",
2422  "THEx_L2_EXT_READ_UNIQUE",
2423  "THEx_L2_EXT_READ_BEATS",
2424  "THEx_L2_EXT_AR_STALL",
2425  "THEx_L2_EXT_AR_CNT_Q1",
2426  "THEx_L2_EXT_AR_CNT_Q2",
2427  "THEx_L2_EXT_AR_CNT_Q3",
2428  "THEx_L2_EXT_RRESP_0_127",
2429  "THEx_L2_EXT_RRESP_128_191",
2430  "THEx_L2_EXT_RRESP_192_255",
2431  "THEx_L2_EXT_RRESP_256_319",
2432  "THEx_L2_EXT_RRESP_320_383",
2433  "THEx_L2_EXT_WRITE",
2434  "THEx_L2_EXT_WRITE_NOSNP_FULL",
2435  "THEx_L2_EXT_WRITE_NOSNP_PTL",
2436  "THEx_L2_EXT_WRITE_SNP_FULL",
2437  "THEx_L2_EXT_WRITE_SNP_PTL",
2438  "THEx_L2_EXT_WRITE_BEATS",
2439  "THEx_L2_EXT_W_STALL",
2440  "THEx_L2_EXT_AW_CNT_Q1",
2441  "THEx_L2_EXT_AW_CNT_Q2",
2442  "THEx_L2_EXT_AW_CNT_Q3",
2443  "THEx_L2_EXT_SNOOP",
2444  "THEx_L2_EXT_SNOOP_STALL",
2445  "THEx_L2_EXT_SNOOP_RESP_CLEAN",
2446  "THEx_L2_EXT_SNOOP_RESP_DATA",
2447  "THEx_L2_EXT_SNOOP_INTERNAL",
2448  "",
2449  "",
2450  "",
2451  "",
2452  "",
2453  "",
2454  "",
2455 };
2456 
2457 static const char *const hardware_counters_mali_tMIx[] =
2458 {
2459  /* Performance counters for the Job Manager */
2460  "",
2461  "",
2462  "",
2463  "",
2464  "TMIx_MESSAGES_SENT",
2465  "TMIx_MESSAGES_RECEIVED",
2466  "TMIx_GPU_ACTIVE",
2467  "TMIx_IRQ_ACTIVE",
2468  "TMIx_JS0_JOBS",
2469  "TMIx_JS0_TASKS",
2470  "TMIx_JS0_ACTIVE",
2471  "",
2472  "TMIx_JS0_WAIT_READ",
2473  "TMIx_JS0_WAIT_ISSUE",
2474  "TMIx_JS0_WAIT_DEPEND",
2475  "TMIx_JS0_WAIT_FINISH",
2476  "TMIx_JS1_JOBS",
2477  "TMIx_JS1_TASKS",
2478  "TMIx_JS1_ACTIVE",
2479  "",
2480  "TMIx_JS1_WAIT_READ",
2481  "TMIx_JS1_WAIT_ISSUE",
2482  "TMIx_JS1_WAIT_DEPEND",
2483  "TMIx_JS1_WAIT_FINISH",
2484  "TMIx_JS2_JOBS",
2485  "TMIx_JS2_TASKS",
2486  "TMIx_JS2_ACTIVE",
2487  "",
2488  "TMIx_JS2_WAIT_READ",
2489  "TMIx_JS2_WAIT_ISSUE",
2490  "TMIx_JS2_WAIT_DEPEND",
2491  "TMIx_JS2_WAIT_FINISH",
2492  "",
2493  "",
2494  "",
2495  "",
2496  "",
2497  "",
2498  "",
2499  "",
2500  "",
2501  "",
2502  "",
2503  "",
2504  "",
2505  "",
2506  "",
2507  "",
2508  "",
2509  "",
2510  "",
2511  "",
2512  "",
2513  "",
2514  "",
2515  "",
2516  "",
2517  "",
2518  "",
2519  "",
2520  "",
2521  "",
2522  "",
2523  "",
2524 
2525  /* Performance counters for the Tiler */
2526  "",
2527  "",
2528  "",
2529  "",
2530  "TMIx_TILER_ACTIVE",
2531  "TMIx_JOBS_PROCESSED",
2532  "TMIx_TRIANGLES",
2533  "TMIx_LINES",
2534  "TMIx_POINTS",
2535  "TMIx_FRONT_FACING",
2536  "TMIx_BACK_FACING",
2537  "TMIx_PRIM_VISIBLE",
2538  "TMIx_PRIM_CULLED",
2539  "TMIx_PRIM_CLIPPED",
2540  "TMIx_PRIM_SAT_CULLED",
2541  "",
2542  "",
2543  "TMIx_BUS_READ",
2544  "",
2545  "TMIx_BUS_WRITE",
2546  "TMIx_LOADING_DESC",
2547  "TMIx_IDVS_POS_SHAD_REQ",
2548  "TMIx_IDVS_POS_SHAD_WAIT",
2549  "TMIx_IDVS_POS_SHAD_STALL",
2550  "TMIx_IDVS_POS_FIFO_FULL",
2551  "TMIx_PREFETCH_STALL",
2552  "TMIx_VCACHE_HIT",
2553  "TMIx_VCACHE_MISS",
2554  "TMIx_VCACHE_LINE_WAIT",
2555  "TMIx_VFETCH_POS_READ_WAIT",
2556  "TMIx_VFETCH_VERTEX_WAIT",
2557  "TMIx_VFETCH_STALL",
2558  "TMIx_PRIMASSY_STALL",
2559  "TMIx_BBOX_GEN_STALL",
2560  "TMIx_IDVS_VBU_HIT",
2561  "TMIx_IDVS_VBU_MISS",
2562  "TMIx_IDVS_VBU_LINE_DEALLOCATE",
2563  "TMIx_IDVS_VAR_SHAD_REQ",
2564  "TMIx_IDVS_VAR_SHAD_STALL",
2565  "TMIx_BINNER_STALL",
2566  "TMIx_ITER_STALL",
2567  "TMIx_COMPRESS_MISS",
2568  "TMIx_COMPRESS_STALL",
2569  "TMIx_PCACHE_HIT",
2570  "TMIx_PCACHE_MISS",
2571  "TMIx_PCACHE_MISS_STALL",
2572  "TMIx_PCACHE_EVICT_STALL",
2573  "TMIx_PMGR_PTR_WR_STALL",
2574  "TMIx_PMGR_PTR_RD_STALL",
2575  "TMIx_PMGR_CMD_WR_STALL",
2576  "TMIx_WRBUF_ACTIVE",
2577  "TMIx_WRBUF_HIT",
2578  "TMIx_WRBUF_MISS",
2579  "TMIx_WRBUF_NO_FREE_LINE_STALL",
2580  "TMIx_WRBUF_NO_AXI_ID_STALL",
2581  "TMIx_WRBUF_AXI_STALL",
2582  "",
2583  "",
2584  "",
2585  "TMIx_UTLB_TRANS",
2586  "TMIx_UTLB_TRANS_HIT",
2587  "TMIx_UTLB_TRANS_STALL",
2588  "TMIx_UTLB_TRANS_MISS_DELAY",
2589  "TMIx_UTLB_MMU_REQ",
2590 
2591  /* Performance counters for the Shader Core */
2592  "",
2593  "",
2594  "",
2595  "",
2596  "TMIx_FRAG_ACTIVE",
2597  "TMIx_FRAG_PRIMITIVES",
2598  "TMIx_FRAG_PRIM_RAST",
2599  "TMIx_FRAG_FPK_ACTIVE",
2600  "TMIx_FRAG_STARVING",
2601  "TMIx_FRAG_WARPS",
2602  "TMIx_FRAG_PARTIAL_WARPS",
2603  "TMIx_FRAG_QUADS_RAST",
2604  "TMIx_FRAG_QUADS_EZS_TEST",
2605  "TMIx_FRAG_QUADS_EZS_UPDATE",
2606  "TMIx_FRAG_QUADS_EZS_KILL",
2607  "TMIx_FRAG_LZS_TEST",
2608  "TMIx_FRAG_LZS_KILL",
2609  "",
2610  "TMIx_FRAG_PTILES",
2611  "TMIx_FRAG_TRANS_ELIM",
2612  "TMIx_QUAD_FPK_KILLER",
2613  "",
2614  "TMIx_COMPUTE_ACTIVE",
2615  "TMIx_COMPUTE_TASKS",
2616  "TMIx_COMPUTE_WARPS",
2617  "TMIx_COMPUTE_STARVING",
2618  "TMIx_EXEC_CORE_ACTIVE",
2619  "TMIx_EXEC_ACTIVE",
2620  "TMIx_EXEC_INSTR_COUNT",
2621  "TMIx_EXEC_INSTR_DIVERGED",
2622  "TMIx_EXEC_INSTR_STARVING",
2623  "TMIx_ARITH_INSTR_SINGLE_FMA",
2624  "TMIx_ARITH_INSTR_DOUBLE",
2625  "TMIx_ARITH_INSTR_MSG",
2626  "TMIx_ARITH_INSTR_MSG_ONLY",
2627  "TMIx_TEX_INSTR",
2628  "TMIx_TEX_INSTR_MIPMAP",
2629  "TMIx_TEX_INSTR_COMPRESSED",
2630  "TMIx_TEX_INSTR_3D",
2631  "TMIx_TEX_INSTR_TRILINEAR",
2632  "TMIx_TEX_COORD_ISSUE",
2633  "TMIx_TEX_COORD_STALL",
2634  "TMIx_TEX_STARVE_CACHE",
2635  "TMIx_TEX_STARVE_FILTER",
2636  "TMIx_LS_MEM_READ_FULL",
2637  "TMIx_LS_MEM_READ_SHORT",
2638  "TMIx_LS_MEM_WRITE_FULL",
2639  "TMIx_LS_MEM_WRITE_SHORT",
2640  "TMIx_LS_MEM_ATOMIC",
2641  "TMIx_VARY_INSTR",
2642  "TMIx_VARY_SLOT_32",
2643  "TMIx_VARY_SLOT_16",
2644  "TMIx_ATTR_INSTR",
2645  "TMIx_ARITH_INSTR_FP_MUL",
2646  "TMIx_BEATS_RD_FTC",
2647  "TMIx_BEATS_RD_FTC_EXT",
2648  "TMIx_BEATS_RD_LSC",
2649  "TMIx_BEATS_RD_LSC_EXT",
2650  "TMIx_BEATS_RD_TEX",
2651  "TMIx_BEATS_RD_TEX_EXT",
2652  "TMIx_BEATS_RD_OTHER",
2653  "TMIx_BEATS_WR_LSC",
2654  "TMIx_BEATS_WR_TIB",
2655  "",
2656 
2657  /* Performance counters for the Memory System */
2658  "",
2659  "",
2660  "",
2661  "",
2662  "TMIx_MMU_REQUESTS",
2663  "",
2664  "",
2665  "",
2666  "",
2667  "",
2668  "",
2669  "",
2670  "",
2671  "",
2672  "",
2673  "",
2674  "TMIx_L2_RD_MSG_IN",
2675  "TMIx_L2_RD_MSG_IN_STALL",
2676  "TMIx_L2_WR_MSG_IN",
2677  "TMIx_L2_WR_MSG_IN_STALL",
2678  "TMIx_L2_SNP_MSG_IN",
2679  "TMIx_L2_SNP_MSG_IN_STALL",
2680  "TMIx_L2_RD_MSG_OUT",
2681  "TMIx_L2_RD_MSG_OUT_STALL",
2682  "TMIx_L2_WR_MSG_OUT",
2683  "TMIx_L2_ANY_LOOKUP",
2684  "TMIx_L2_READ_LOOKUP",
2685  "TMIx_L2_WRITE_LOOKUP",
2686  "TMIx_L2_EXT_SNOOP_LOOKUP",
2687  "TMIx_L2_EXT_READ",
2688  "TMIx_L2_EXT_READ_NOSNP",
2689  "TMIx_L2_EXT_READ_UNIQUE",
2690  "TMIx_L2_EXT_READ_BEATS",
2691  "TMIx_L2_EXT_AR_STALL",
2692  "TMIx_L2_EXT_AR_CNT_Q1",
2693  "TMIx_L2_EXT_AR_CNT_Q2",
2694  "TMIx_L2_EXT_AR_CNT_Q3",
2695  "TMIx_L2_EXT_RRESP_0_127",
2696  "TMIx_L2_EXT_RRESP_128_191",
2697  "TMIx_L2_EXT_RRESP_192_255",
2698  "TMIx_L2_EXT_RRESP_256_319",
2699  "TMIx_L2_EXT_RRESP_320_383",
2700  "TMIx_L2_EXT_WRITE",
2701  "TMIx_L2_EXT_WRITE_NOSNP_FULL",
2702  "TMIx_L2_EXT_WRITE_NOSNP_PTL",
2703  "TMIx_L2_EXT_WRITE_SNP_FULL",
2704  "TMIx_L2_EXT_WRITE_SNP_PTL",
2705  "TMIx_L2_EXT_WRITE_BEATS",
2706  "TMIx_L2_EXT_W_STALL",
2707  "TMIx_L2_EXT_AW_CNT_Q1",
2708  "TMIx_L2_EXT_AW_CNT_Q2",
2709  "TMIx_L2_EXT_AW_CNT_Q3",
2710  "TMIx_L2_EXT_SNOOP",
2711  "TMIx_L2_EXT_SNOOP_STALL",
2712  "TMIx_L2_EXT_SNOOP_RESP_CLEAN",
2713  "TMIx_L2_EXT_SNOOP_RESP_DATA",
2714  "TMIx_L2_EXT_SNOOP_INTERNAL",
2715  "",
2716  "",
2717  "",
2718  "",
2719  "",
2720  "",
2721  "",
2722 };
2723 
2724 static const char *const hardware_counters_mali_tSIx[] =
2725 {
2726  /* Performance counters for the Job Manager */
2727  "",
2728  "",
2729  "",
2730  "",
2731  "TSIx_MESSAGES_SENT",
2732  "TSIx_MESSAGES_RECEIVED",
2733  "TSIx_GPU_ACTIVE",
2734  "TSIx_IRQ_ACTIVE",
2735  "TSIx_JS0_JOBS",
2736  "TSIx_JS0_TASKS",
2737  "TSIx_JS0_ACTIVE",
2738  "",
2739  "TSIx_JS0_WAIT_READ",
2740  "TSIx_JS0_WAIT_ISSUE",
2741  "TSIx_JS0_WAIT_DEPEND",
2742  "TSIx_JS0_WAIT_FINISH",
2743  "TSIx_JS1_JOBS",
2744  "TSIx_JS1_TASKS",
2745  "TSIx_JS1_ACTIVE",
2746  "",
2747  "TSIx_JS1_WAIT_READ",
2748  "TSIx_JS1_WAIT_ISSUE",
2749  "TSIx_JS1_WAIT_DEPEND",
2750  "TSIx_JS1_WAIT_FINISH",
2751  "TSIx_JS2_JOBS",
2752  "TSIx_JS2_TASKS",
2753  "TSIx_JS2_ACTIVE",
2754  "",
2755  "TSIx_JS2_WAIT_READ",
2756  "TSIx_JS2_WAIT_ISSUE",
2757  "TSIx_JS2_WAIT_DEPEND",
2758  "TSIx_JS2_WAIT_FINISH",
2759  "",
2760  "",
2761  "",
2762  "",
2763  "",
2764  "",
2765  "",
2766  "",
2767  "",
2768  "",
2769  "",
2770  "",
2771  "",
2772  "",
2773  "",
2774  "",
2775  "",
2776  "",
2777  "",
2778  "",
2779  "",
2780  "",
2781  "",
2782  "",
2783  "",
2784  "",
2785  "",
2786  "",
2787  "",
2788  "",
2789  "",
2790  "",
2791 
2792  /* Performance counters for the Tiler */
2793  "",
2794  "",
2795  "",
2796  "",
2797  "TSIx_TILER_ACTIVE",
2798  "TSIx_JOBS_PROCESSED",
2799  "TSIx_TRIANGLES",
2800  "TSIx_LINES",
2801  "TSIx_POINTS",
2802  "TSIx_FRONT_FACING",
2803  "TSIx_BACK_FACING",
2804  "TSIx_PRIM_VISIBLE",
2805  "TSIx_PRIM_CULLED",
2806  "TSIx_PRIM_CLIPPED",
2807  "TSIx_PRIM_SAT_CULLED",
2808  "",
2809  "",
2810  "TSIx_BUS_READ",
2811  "",
2812  "TSIx_BUS_WRITE",
2813  "TSIx_LOADING_DESC",
2814  "",
2815  "",
2816  "",
2817  "",
2818  "TSIx_PREFETCH_STALL",
2819  "TSIx_VCACHE_HIT",
2820  "TSIx_VCACHE_MISS",
2821  "TSIx_VCACHE_LINE_WAIT",
2822  "TSIx_VFETCH_POS_READ_WAIT",
2823  "TSIx_VFETCH_VERTEX_WAIT",
2824  "TSIx_VFETCH_STALL",
2825  "TSIx_PRIMASSY_STALL",
2826  "TSIx_BBOX_GEN_STALL",
2827  "",
2828  "",
2829  "",
2830  "",
2831  "",
2832  "TSIx_BINNER_STALL",
2833  "TSIx_ITER_STALL",
2834  "TSIx_COMPRESS_MISS",
2835  "TSIx_COMPRESS_STALL",
2836  "TSIx_PCACHE_HIT",
2837  "TSIx_PCACHE_MISS",
2838  "TSIx_PCACHE_MISS_STALL",
2839  "TSIx_PCACHE_EVICT_STALL",
2840  "TSIx_PMGR_PTR_WR_STALL",
2841  "TSIx_PMGR_PTR_RD_STALL",
2842  "TSIx_PMGR_CMD_WR_STALL",
2843  "TSIx_WRBUF_ACTIVE",
2844  "TSIx_WRBUF_HIT",
2845  "TSIx_WRBUF_MISS",
2846  "TSIx_WRBUF_NO_FREE_LINE_STALL",
2847  "TSIx_WRBUF_NO_AXI_ID_STALL",
2848  "TSIx_WRBUF_AXI_STALL",
2849  "",
2850  "",
2851  "",
2852  "TSIx_UTLB_TRANS",
2853  "TSIx_UTLB_TRANS_HIT",
2854  "TSIx_UTLB_TRANS_STALL",
2855  "TSIx_UTLB_TRANS_MISS_DELAY",
2856  "TSIx_UTLB_MMU_REQ",
2857 
2858  /* Performance counters for the Shader Core */
2859  "",
2860  "",
2861  "",
2862  "",
2863  "TSIx_FRAG_ACTIVE",
2864  "TSIx_FRAG_PRIMITIVES",
2865  "TSIx_FRAG_PRIM_RAST",
2866  "TSIx_FRAG_FPK_ACTIVE",
2867  "TSIx_FRAG_STARVING",
2868  "TSIx_FRAG_WARPS",
2869  "TSIx_FRAG_PARTIAL_WARPS",
2870  "TSIx_FRAG_QUADS_RAST",
2871  "TSIx_FRAG_QUADS_EZS_TEST",
2872  "TSIx_FRAG_QUADS_EZS_UPDATE",
2873  "TSIx_FRAG_QUADS_EZS_KILL",
2874  "TSIx_FRAG_LZS_TEST",
2875  "TSIx_FRAG_LZS_KILL",
2876  "",
2877  "TSIx_FRAG_PTILES",
2878  "TSIx_FRAG_TRANS_ELIM",
2879  "TSIx_QUAD_FPK_KILLER",
2880  "",
2881  "TSIx_COMPUTE_ACTIVE",
2882  "TSIx_COMPUTE_TASKS",
2883  "TSIx_COMPUTE_WARPS",
2884  "TSIx_COMPUTE_STARVING",
2885  "TSIx_EXEC_CORE_ACTIVE",
2886  "TSIx_EXEC_ACTIVE",
2887  "TSIx_EXEC_INSTR_COUNT",
2888  "TSIx_EXEC_INSTR_DIVERGED",
2889  "TSIx_EXEC_INSTR_STARVING",
2890  "TSIx_ARITH_INSTR_SINGLE_FMA",
2891  "TSIx_ARITH_INSTR_DOUBLE",
2892  "TSIx_ARITH_INSTR_MSG",
2893  "TSIx_ARITH_INSTR_MSG_ONLY",
2894  "TSIx_TEX_INSTR",
2895  "TSIx_TEX_INSTR_MIPMAP",
2896  "TSIx_TEX_INSTR_COMPRESSED",
2897  "TSIx_TEX_INSTR_3D",
2898  "TSIx_TEX_INSTR_TRILINEAR",
2899  "TSIx_TEX_COORD_ISSUE",
2900  "TSIx_TEX_COORD_STALL",
2901  "TSIx_TEX_STARVE_CACHE",
2902  "TSIx_TEX_STARVE_FILTER",
2903  "TSIx_LS_MEM_READ_FULL",
2904  "TSIx_LS_MEM_READ_SHORT",
2905  "TSIx_LS_MEM_WRITE_FULL",
2906  "TSIx_LS_MEM_WRITE_SHORT",
2907  "TSIx_LS_MEM_ATOMIC",
2908  "TSIx_VARY_INSTR",
2909  "TSIx_VARY_SLOT_32",
2910  "TSIx_VARY_SLOT_16",
2911  "TSIx_ATTR_INSTR",
2912  "TSIx_ARITH_INSTR_FP_MUL",
2913  "TSIx_BEATS_RD_FTC",
2914  "TSIx_BEATS_RD_FTC_EXT",
2915  "TSIx_BEATS_RD_LSC",
2916  "TSIx_BEATS_RD_LSC_EXT",
2917  "TSIx_BEATS_RD_TEX",
2918  "TSIx_BEATS_RD_TEX_EXT",
2919  "TSIx_BEATS_RD_OTHER",
2920  "TSIx_BEATS_WR_LSC",
2921  "TSIx_BEATS_WR_TIB",
2922  "",
2923 
2924  /* Performance counters for the Memory System */
2925  "",
2926  "",
2927  "",
2928  "",
2929  "TSIx_MMU_REQUESTS",
2930  "",
2931  "",
2932  "",
2933  "",
2934  "",
2935  "",
2936  "",
2937  "",
2938  "",
2939  "",
2940  "",
2941  "TSIx_L2_RD_MSG_IN",
2942  "TSIx_L2_RD_MSG_IN_STALL",
2943  "TSIx_L2_WR_MSG_IN",
2944  "TSIx_L2_WR_MSG_IN_STALL",
2945  "TSIx_L2_SNP_MSG_IN",
2946  "TSIx_L2_SNP_MSG_IN_STALL",
2947  "TSIx_L2_RD_MSG_OUT",
2948  "TSIx_L2_RD_MSG_OUT_STALL",
2949  "TSIx_L2_WR_MSG_OUT",
2950  "TSIx_L2_ANY_LOOKUP",
2951  "TSIx_L2_READ_LOOKUP",
2952  "TSIx_L2_WRITE_LOOKUP",
2953  "TSIx_L2_EXT_SNOOP_LOOKUP",
2954  "TSIx_L2_EXT_READ",
2955  "TSIx_L2_EXT_READ_NOSNP",
2956  "TSIx_L2_EXT_READ_UNIQUE",
2957  "TSIx_L2_EXT_READ_BEATS",
2958  "TSIx_L2_EXT_AR_STALL",
2959  "TSIx_L2_EXT_AR_CNT_Q1",
2960  "TSIx_L2_EXT_AR_CNT_Q2",
2961  "TSIx_L2_EXT_AR_CNT_Q3",
2962  "TSIx_L2_EXT_RRESP_0_127",
2963  "TSIx_L2_EXT_RRESP_128_191",
2964  "TSIx_L2_EXT_RRESP_192_255",
2965  "TSIx_L2_EXT_RRESP_256_319",
2966  "TSIx_L2_EXT_RRESP_320_383",
2967  "TSIx_L2_EXT_WRITE",
2968  "TSIx_L2_EXT_WRITE_NOSNP_FULL",
2969  "TSIx_L2_EXT_WRITE_NOSNP_PTL",
2970  "TSIx_L2_EXT_WRITE_SNP_FULL",
2971  "TSIx_L2_EXT_WRITE_SNP_PTL",
2972  "TSIx_L2_EXT_WRITE_BEATS",
2973  "TSIx_L2_EXT_W_STALL",
2974  "TSIx_L2_EXT_AW_CNT_Q1",
2975  "TSIx_L2_EXT_AW_CNT_Q2",
2976  "TSIx_L2_EXT_AW_CNT_Q3",
2977  "TSIx_L2_EXT_SNOOP",
2978  "TSIx_L2_EXT_SNOOP_STALL",
2979  "TSIx_L2_EXT_SNOOP_RESP_CLEAN",
2980  "TSIx_L2_EXT_SNOOP_RESP_DATA",
2981  "TSIx_L2_EXT_SNOOP_INTERNAL",
2982  "",
2983  "",
2984  "",
2985  "",
2986  "",
2987  "",
2988  "",
2989 };
2990 
2991 enum
2992 {
2993  /* product id masks for old and new versions of the id field. NB: the T60x must be tested before anything else as it could exceptionally be
2994  * treated as a new style of id with produce code 0x6006 */
2995  PRODUCT_ID_MASK_OLD = 0xffff,
2996  PRODUCT_ID_MASK_NEW = 0xf00f,
2997  /* Old style product ids */
2998  PRODUCT_ID_T60X = 0x6956,
2999  PRODUCT_ID_T62X = 0x0620,
3000  PRODUCT_ID_T72X = 0x0720,
3001  PRODUCT_ID_T76X = 0x0750,
3002  PRODUCT_ID_T82X = 0x0820,
3003  PRODUCT_ID_T83X = 0x0830,
3004  PRODUCT_ID_T86X = 0x0860,
3005  PRODUCT_ID_TFRX = 0x0880,
3006  /* New style product ids */
3007  PRODUCT_ID_TMIX = 0x6000,
3008  PRODUCT_ID_THEX = 0x6001,
3009  PRODUCT_ID_TSIX = 0x7000
3010 };
3011 
3012 struct CounterMapping
3013 {
3014  uint32_t product_mask;
3015  uint32_t product_id;
3016  const char *const *names_lut;
3017 };
3018 
3019 static const CounterMapping products[] =
3020 {
3021  {
3022  PRODUCT_ID_MASK_OLD, PRODUCT_ID_T60X, hardware_counters_mali_t60x,
3023  },
3024  {
3025  PRODUCT_ID_MASK_OLD, PRODUCT_ID_T62X, hardware_counters_mali_t62x,
3026  },
3027  {
3028  PRODUCT_ID_MASK_OLD, PRODUCT_ID_T72X, hardware_counters_mali_t72x,
3029  },
3030  {
3031  PRODUCT_ID_MASK_OLD, PRODUCT_ID_T76X, hardware_counters_mali_t76x,
3032  },
3033  {
3034  PRODUCT_ID_MASK_OLD, PRODUCT_ID_T82X, hardware_counters_mali_t82x,
3035  },
3036  {
3037  PRODUCT_ID_MASK_OLD, PRODUCT_ID_T83X, hardware_counters_mali_t83x,
3038  },
3039  {
3040  PRODUCT_ID_MASK_OLD, PRODUCT_ID_T86X, hardware_counters_mali_t86x,
3041  },
3042  {
3043  PRODUCT_ID_MASK_OLD, PRODUCT_ID_TFRX, hardware_counters_mali_t88x,
3044  },
3045  {
3046  PRODUCT_ID_MASK_NEW, PRODUCT_ID_TMIX, hardware_counters_mali_tMIx,
3047  },
3048  {
3049  PRODUCT_ID_MASK_NEW, PRODUCT_ID_THEX, hardware_counters_mali_tHEx,
3050  },
3051  {
3052  PRODUCT_ID_MASK_NEW, PRODUCT_ID_TSIX, hardware_counters_mali_tSIx,
3053  },
3054 };
3055 
3056 enum
3057 {
3058  NUM_PRODUCTS = sizeof(products) / sizeof(products[0])
3059 };
3060 } // namespace mali_userspace
3061 
3062 #endif /* DOXYGEN_SKIP_THIS */
3063 
3064 #endif /* ARM_COMPUTE_TEST_HWC_NAMES */