24.04
sme_interleave2VL_bf16_bf16.hpp
Go to the documentation of this file.
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/*
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* Copyright (c) 2022-2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#if defined(ARM_COMPUTE_ENABLE_SME)
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template
<>
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void
interleave_block<2, 1, VLType::SME, false>(
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bfloat16
* &out,
const
bfloat16
*
const
*in,
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size_t
width,
size_t
height,
size_t
row_offset,
bool
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)
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{
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__asm__ __volatile__(
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".inst 0xd503477f // SMSTART ZA\n"
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"cnth x28\n"
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"cmp %x[height], x28\n"
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"cnth x27\n"
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"csel x28, %x[height], x28, LT\n"
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"mov x26, #0x0\n"
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"ptrue p13.s\n"
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"sub x28, x28, #0x1\n"
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"whilelt p12.h, XZR, %x[height]\n"
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"whilelt p11.h, x27, %x[height]\n"
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"mov x25, %x[row_offset]\n"
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"mov x24, %x[out]\n"
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"whilelt p10.h, x26, %x[width]\n"
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"whilelt p9.h, x26, %x[width]\n"
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"whilelt p8.h, x26, %x[width]\n"
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"1:"
// Width loop
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"add x23, %x[in], XZR, LSL #3\n"
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"add x20, %x[in], x27, LSL #3\n"
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"ldr x22, [x23], #0x8\n"
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"mov x12, #0x0\n"
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"ldr x21, [x20], #0x8\n"
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"cbz x28, 3f\n"
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"2:"
// Loads: Loop
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".inst 0x25286581 // psel p1.h, p9.h/Z, p12.h[w12]\n"
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".inst 0x25286160 // psel p0.h, p8.h/Z, p11.h[w12]\n"
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".inst 0xe05906c0 // ld1h { za0h.h[x12] }, p1/Z, [x22, x25, LSL #1]\n"
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"ldr x22, [x23], #0x8\n"
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".inst 0xe05902a8 // ld1h { za1h.h[x12] }, p0/Z, [x21, x25, LSL #1]\n"
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"add x12, x12, #0x2\n"
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"cmp x12, x28, LSL #1\n"
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"ldr x21, [x20], #0x8\n"
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"blt 2b\n"
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"3:"
// Loads: Tail
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"sub x20, %x[width], x26\n"
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".inst 0x25286580 // psel p0.h, p9.h/Z, p12.h[w12]\n"
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".inst 0xe05902c0 // ld1h { za0h.h[x12] }, p0/Z, [x22, x25, LSL #1]\n"
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".inst 0x25286160 // psel p0.h, p8.h/Z, p11.h[w12]\n"
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"cmp x20, x27\n"
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".inst 0xe05902a8 // ld1h { za1h.h[x12] }, p0/Z, [x21, x25, LSL #1]\n"
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"mov x12, #0x0\n"
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"csel x20, x20, x27, LT\n"
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"4:"
// Stores: Loop
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".inst 0x25287540 // psel p0.h, p13.h/Z, p10.h[w12]\n"
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".inst 0xe07f8300 // st1h { za0v.h[x12] }, p0/Z, [x24, XZR, LSL #1]\n"
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".inst 0x25287540 // psel p0.h, p13.h/Z, p10.h[w12]\n"
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".inst 0xe07b8308 // st1h { za1v.h[x12] }, p0/Z, [x24, x27, LSL #1]\n"
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"add x12, x12, #0x1\n"
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"cmp x12, x20\n"
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"addvl x24, x24, #4\n"
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"blt 4b\n"
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"inch x26\n"
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"whilelt p10.h, x26, %x[width]\n"
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"whilelt p9.h, x26, %x[width]\n"
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"whilelt p8.h, x26, %x[width]\n"
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"inch x25\n"
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"b.any 1b\n"
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"mov %x[out], x24\n"
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".inst 0xd503467f // SMSTOP\n"
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: [out]
"+&r"
(out)
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: [height]
"r"
(height), [in]
"r"
(in), [row_offset]
"r"
(row_offset), [width]
"r"
(width)
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:
"cc"
,
"memory"
,
"p0"
,
"p1"
,
"p2"
,
"p3"
,
"p4"
,
"p5"
,
"p6"
,
"p7"
,
"p8"
,
"p9"
,
"p10"
,
"p11"
,
"p12"
,
"p13"
,
"p14"
,
"p15"
,
"x12"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"x24"
,
"x25"
,
"x26"
,
"x27"
,
"x28"
,
"z0"
,
"z1"
,
"z2"
,
"z3"
,
"z4"
,
"z5"
,
"z6"
,
"z7"
,
"z8"
,
"z9"
,
"z10"
,
"z11"
,
"z12"
,
"z13"
,
"z14"
,
"z15"
,
"z16"
,
"z17"
,
"z18"
,
"z19"
,
"z20"
,
"z21"
,
"z22"
,
"z23"
,
"z24"
,
"z25"
,
"z26"
,
"z27"
,
"z28"
,
"z29"
,
"z30"
,
"z31"
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);
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}
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#endif // defined(ARM_COMPUTE_ENABLE_SME)
arm_gemm::bfloat16
arm_compute::bfloat16 bfloat16
Definition:
bfloat.hpp:30
src
core
NEON
kernels
arm_gemm
indirect-interleaves
sme_interleave2VL_bf16_bf16.hpp
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