27 #if defined(ARM_COMPUTE_ENABLE_SME)
31 void sme_transpose_interleave_16VL_1x4(uint8_t *out,
const uint8_t *in,
size_t width,
size_t in_stride,
size_t height)
33 uint8_t *pad_row =
reinterpret_cast<uint8_t *
>(alloca(width *
sizeof(uint8_t)));
36 memset(pad_row, 0, width *
sizeof(uint8_t));
39 size_t out_stride = 16 * roundup<size_t>(height, 4) * sme::get_vector_length<uint32_t>();
42 ".inst 0xd503477f // SMSTART ZA\n"
46 "add x25, x26, %x[in_stride]\n"
47 "add x24, x25, %x[in_stride]\n"
48 "add x23, x24, %x[in_stride]\n"
49 "cmp %x[height], #0x3\n"
50 "add %x[in], x23, %x[in_stride]\n"
51 "csel x23, x23, %x[pad_row], GT\n"
52 "csel x24, x24, %x[pad_row], GE\n"
53 "cmp %x[height], #0x1\n"
55 "csel x25, x25, %x[pad_row], GT\n"
56 "sub %x[height], %x[height], #0x4\n"
57 "mov x21, %x[width]\n"
60 "whilelt p3.b, XZR, x20\n"
61 "ld1b { z20.b }, p3/Z, [x26]\n"
63 "whilelt p2.b, XZR, x20\n"
64 "ld1b { z18.b }, p2/Z, [x26, #1, MUL VL]\n"
66 "whilelt p1.b, XZR, x20\n"
67 "ld1b { z17.b }, p3/Z, [x25]\n"
69 "whilelt p0.b, XZR, x20\n"
70 "ld1b { z19.b }, p2/Z, [x25, #1, MUL VL]\n"
71 "ld1b { z16.b }, p3/Z, [x24]\n"
72 "zip1 z25.b, z20.b, z16.b\n"
73 "zip2 z24.b, z20.b, z16.b\n"
75 "ld1b { z16.b }, p2/Z, [x24, #1, MUL VL]\n"
76 "zip1 z22.b, z18.b, z16.b\n"
77 "zip2 z21.b, z18.b, z16.b\n"
78 "decw x21, ALL, MUL #16\n"
79 "ld1b { z16.b }, p3/Z, [x23]\n"
80 "zip1 z18.b, z17.b, z16.b\n"
81 "zip2 z17.b, z17.b, z16.b\n"
83 "ld1b { z16.b }, p2/Z, [x23, #1, MUL VL]\n"
84 "zip1 z20.b, z19.b, z16.b\n"
85 "zip2 z16.b, z19.b, z16.b\n"
86 "add x22, x22, %x[out_stride]\n"
87 "ld1b { z19.b }, p1/Z, [x26, #2, MUL VL]\n"
88 "zip1 z23.b, z25.b, z18.b\n"
89 "zip2 z0.b, z25.b, z18.b\n"
90 "ld1b { z18.b }, p0/Z, [x26, #3, MUL VL]\n"
91 "zip1 z31.b, z24.b, z17.b\n"
92 "zip2 z30.b, z24.b, z17.b\n"
93 "addvl x26, x26, #4\n"
94 "ld1b { z17.b }, p1/Z, [x25, #2, MUL VL]\n"
95 "zip1 z29.b, z22.b, z20.b\n"
96 "zip2 z28.b, z22.b, z20.b\n"
97 "ld1b { z22.b }, p0/Z, [x25, #3, MUL VL]\n"
98 "zip1 z27.b, z21.b, z16.b\n"
99 "zip2 z26.b, z21.b, z16.b\n"
100 "addvl x25, x25, #4\n"
101 "ld1b { z16.b }, p1/Z, [x24, #2, MUL VL]\n"
102 "zip1 z21.b, z19.b, z16.b\n"
103 "zip2 z20.b, z19.b, z16.b\n"
104 "ld1b { z16.b }, p0/Z, [x24, #3, MUL VL]\n"
105 "zip1 z25.b, z18.b, z16.b\n"
106 "zip2 z24.b, z18.b, z16.b\n"
107 "addvl x24, x24, #4\n"
108 "ld1b { z16.b }, p1/Z, [x23, #2, MUL VL]\n"
109 "zip1 z19.b, z17.b, z16.b\n"
110 "zip2 z18.b, z17.b, z16.b\n"
111 "ld1b { z16.b }, p0/Z, [x23, #3, MUL VL]\n"
112 "zip1 z17.b, z22.b, z16.b\n"
113 "zip2 z16.b, z22.b, z16.b\n"
114 "addvl x23, x23, #4\n"
115 "st1b { z23.b }, p4, [x20]\n"
116 "zip1 z23.b, z21.b, z19.b\n"
117 "zip2 z22.b, z21.b, z19.b\n"
118 "st1b { z0.b }, p4, [x20, #1, MUL VL]\n"
119 "zip1 z21.b, z20.b, z18.b\n"
120 "zip2 z20.b, z20.b, z18.b\n"
121 "st1b { z31.b }, p4, [x20, #2, MUL VL]\n"
122 "zip1 z19.b, z25.b, z17.b\n"
123 "zip2 z18.b, z25.b, z17.b\n"
124 "st1b { z30.b }, p4, [x20, #3, MUL VL]\n"
125 "zip1 z17.b, z24.b, z16.b\n"
126 "zip2 z16.b, z24.b, z16.b\n"
127 "st1b { z29.b }, p4, [x20, #4, MUL VL]\n"
128 "st1b { z28.b }, p4, [x20, #5, MUL VL]\n"
129 "st1b { z27.b }, p4, [x20, #6, MUL VL]\n"
130 "st1b { z26.b }, p4, [x20, #7, MUL VL]\n"
131 "addvl x20, x20, #16\n"
132 "st1b { z23.b }, p4, [x20, #-8, MUL VL]\n"
133 "st1b { z22.b }, p4, [x20, #-7, MUL VL]\n"
134 "st1b { z21.b }, p4, [x20, #-6, MUL VL]\n"
135 "st1b { z20.b }, p4, [x20, #-5, MUL VL]\n"
136 "st1b { z19.b }, p4, [x20, #-4, MUL VL]\n"
137 "st1b { z18.b }, p4, [x20, #-3, MUL VL]\n"
138 "st1b { z17.b }, p4, [x20, #-2, MUL VL]\n"
139 "st1b { z16.b }, p4, [x20, #-1, MUL VL]\n"
142 "cmp %x[height], #0x1\n"
143 "addvl %x[out], %x[out], #16\n"
145 ".inst 0xd503467f // SMSTOP\n"
146 : [height]
"+&r" (height), [in]
"+&r" (in), [out]
"+&r" (out)
147 : [in_stride]
"r" (in_stride), [out_stride]
"r" (out_stride), [pad_row]
"r" (pad_row), [width]
"r" (width)
148 :
"cc",
"memory",
"p0",
"p1",
"p2",
"p3",
"p4",
"p5",
"p6",
"p7",
"p8",
"p9",
"p10",
"p11",
"p12",
"p13",
"p14",
"p15",
"x20",
"x21",
"x22",
"x23",
"x24",
"x25",
"x26",
"z0",
"z1",
"z2",
"z3",
"z4",
"z5",
"z6",
"z7",
"z8",
"z9",
"z10",
"z11",
"z12",
"z13",
"z14",
"z15",
"z16",
"z17",
"z18",
"z19",
"z20",
"z21",
"z22",
"z23",
"z24",
"z25",
"z26",
"z27",
"z28",
"z29",
"z30",
"z31"
155 void Transform<16, 4, true, VLType::SME>(
156 uint8_t *out,
const uint8_t *in,
int stride,
int x0,
int xmax,
int k0,
int kmax)
158 sme_transpose_interleave_16VL_1x4(
159 reinterpret_cast<uint8_t *
>(out),
160 reinterpret_cast<const uint8_t *
>(in + k0 * stride + x0),
161 (xmax-x0) *
sizeof(uint8_t) / 1,
162 stride *
sizeof(uint8_t),
168 void Transform<16, 4, true, VLType::SME>(
169 int8_t *out,
const int8_t *in,
int stride,
int x0,
int xmax,
int k0,
int kmax)
171 sme_transpose_interleave_16VL_1x4(
172 reinterpret_cast<uint8_t *
>(out),
173 reinterpret_cast<const uint8_t *
>(in + k0 * stride + x0),
174 (xmax-x0) *
sizeof(int8_t) / 1,
175 stride *
sizeof(int8_t),
181 #endif // defined(ARM_COMPUTE_ENABLE_SME)