27 #if defined(ARM_COMPUTE_ENABLE_SME)
31 void sme_transpose_interleave_16VL_2x2_fp32bf16(
bfloat16 *out,
const float *in,
size_t width,
size_t in_stride,
size_t height)
33 float *pad_row =
reinterpret_cast<float *
>(alloca(width *
sizeof(
float)));
36 memset(pad_row, 0, width *
sizeof(
float));
39 size_t out_stride = 16 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>();
42 ".inst 0xd503477f // SMSTART ZA\n"
46 "add x24, x25, %x[in_stride]\n"
47 "cmp %x[height], #0x1\n"
48 "add %x[in], x24, %x[in_stride]\n"
50 "csel x24, x24, %x[pad_row], GT\n"
51 "sub %x[height], %x[height], #0x2\n"
52 "mov x22, %x[width]\n"
55 "whilelt p1.s, XZR, x21\n"
56 "ld1w { z16.s }, p1/Z, [x25]\n"
57 ".inst 0x658abe00 // bfcvt z0.h, p7/M, z16.s\n"
59 "whilelt p0.s, XZR, x21\n"
60 "ld1w { z16.s }, p0/Z, [x25, #1, MUL VL]\n"
61 ".inst 0x658abe1f // bfcvt z31.h, p7/M, z16.s\n"
63 "whilelt p6.s, XZR, x21\n"
64 "ld1w { z16.s }, p6/Z, [x25, #2, MUL VL]\n"
65 ".inst 0x658abe1e // bfcvt z30.h, p7/M, z16.s\n"
67 "whilelt p5.s, XZR, x21\n"
68 "ld1w { z16.s }, p5/Z, [x25, #3, MUL VL]\n"
69 ".inst 0x658abe1d // bfcvt z29.h, p7/M, z16.s\n"
71 "whilelt p4.s, XZR, x21\n"
72 "ld1w { z16.s }, p4/Z, [x25, #4, MUL VL]\n"
73 ".inst 0x658abe1c // bfcvt z28.h, p7/M, z16.s\n"
75 "whilelt p3.s, XZR, x21\n"
76 "ld1w { z16.s }, p3/Z, [x25, #5, MUL VL]\n"
77 ".inst 0x658abe1b // bfcvt z27.h, p7/M, z16.s\n"
79 "whilelt p2.s, XZR, x21\n"
80 "ld1w { z16.s }, p2/Z, [x25, #6, MUL VL]\n"
81 ".inst 0x658abe1a // bfcvt z26.h, p7/M, z16.s\n"
83 "ld1w { z16.s }, p1/Z, [x24]\n"
84 "whilelt p1.s, XZR, x21\n"
85 ".inst 0x648abe00 // bfcvtnt z0.h, p7/M, z16.s\n"
87 "ld1w { z16.s }, p1/Z, [x25, #7, MUL VL]\n"
88 "addvl x25, x25, #16\n"
89 ".inst 0x658abe19 // bfcvt z25.h, p7/M, z16.s\n"
90 "ld1w { z16.s }, p0/Z, [x24, #1, MUL VL]\n"
91 "whilelt p0.s, XZR, x21\n"
93 ".inst 0x648abe1f // bfcvtnt z31.h, p7/M, z16.s\n"
94 "ld1w { z16.s }, p0/Z, [x25, #-8, MUL VL]\n"
95 ".inst 0x658abe18 // bfcvt z24.h, p7/M, z16.s\n"
97 "decw x22, ALL, MUL #16\n"
98 "ld1w { z16.s }, p6/Z, [x24, #2, MUL VL]\n"
99 "whilelt p6.s, XZR, x21\n"
101 ".inst 0x648abe1e // bfcvtnt z30.h, p7/M, z16.s\n"
102 "ld1w { z16.s }, p6/Z, [x25, #-7, MUL VL]\n"
103 ".inst 0x658abe17 // bfcvt z23.h, p7/M, z16.s\n"
104 "add x23, x23, %x[out_stride]\n"
105 "ld1w { z16.s }, p5/Z, [x24, #3, MUL VL]\n"
106 "whilelt p5.s, XZR, x21\n"
108 ".inst 0x648abe1d // bfcvtnt z29.h, p7/M, z16.s\n"
109 "ld1w { z16.s }, p5/Z, [x25, #-6, MUL VL]\n"
110 ".inst 0x658abe16 // bfcvt z22.h, p7/M, z16.s\n"
111 "ld1w { z16.s }, p4/Z, [x24, #4, MUL VL]\n"
112 "whilelt p4.s, XZR, x21\n"
114 ".inst 0x648abe1c // bfcvtnt z28.h, p7/M, z16.s\n"
115 "ld1w { z16.s }, p4/Z, [x25, #-5, MUL VL]\n"
116 ".inst 0x658abe15 // bfcvt z21.h, p7/M, z16.s\n"
117 "ld1w { z16.s }, p3/Z, [x24, #5, MUL VL]\n"
118 "whilelt p3.s, XZR, x21\n"
120 ".inst 0x648abe1b // bfcvtnt z27.h, p7/M, z16.s\n"
121 "ld1w { z16.s }, p3/Z, [x25, #-4, MUL VL]\n"
122 ".inst 0x658abe14 // bfcvt z20.h, p7/M, z16.s\n"
123 "ld1w { z16.s }, p2/Z, [x24, #6, MUL VL]\n"
124 "whilelt p2.s, XZR, x21\n"
126 ".inst 0x648abe1a // bfcvtnt z26.h, p7/M, z16.s\n"
127 "ld1w { z16.s }, p2/Z, [x25, #-3, MUL VL]\n"
128 ".inst 0x658abe13 // bfcvt z19.h, p7/M, z16.s\n"
129 "ld1w { z16.s }, p1/Z, [x24, #7, MUL VL]\n"
130 "whilelt p1.s, XZR, x21\n"
132 ".inst 0x648abe19 // bfcvtnt z25.h, p7/M, z16.s\n"
133 "ld1w { z16.s }, p1/Z, [x25, #-2, MUL VL]\n"
134 "addvl x24, x24, #16\n"
135 ".inst 0x658abe12 // bfcvt z18.h, p7/M, z16.s\n"
136 "ld1w { z16.s }, p0/Z, [x24, #-8, MUL VL]\n"
137 "whilelt p0.s, XZR, x21\n"
139 ".inst 0x648abe18 // bfcvtnt z24.h, p7/M, z16.s\n"
140 "ld1w { z16.s }, p0/Z, [x25, #-1, MUL VL]\n"
141 ".inst 0x658abe11 // bfcvt z17.h, p7/M, z16.s\n"
142 "ld1w { z16.s }, p6/Z, [x24, #-7, MUL VL]\n"
143 ".inst 0x648abe17 // bfcvtnt z23.h, p7/M, z16.s\n"
144 "ld1w { z16.s }, p5/Z, [x24, #-6, MUL VL]\n"
145 ".inst 0x648abe16 // bfcvtnt z22.h, p7/M, z16.s\n"
146 "ld1w { z16.s }, p4/Z, [x24, #-5, MUL VL]\n"
147 ".inst 0x648abe15 // bfcvtnt z21.h, p7/M, z16.s\n"
148 "ld1w { z16.s }, p3/Z, [x24, #-4, MUL VL]\n"
149 ".inst 0x648abe14 // bfcvtnt z20.h, p7/M, z16.s\n"
150 "ld1w { z16.s }, p2/Z, [x24, #-3, MUL VL]\n"
151 ".inst 0x648abe13 // bfcvtnt z19.h, p7/M, z16.s\n"
152 "ld1w { z16.s }, p1/Z, [x24, #-2, MUL VL]\n"
153 ".inst 0x648abe12 // bfcvtnt z18.h, p7/M, z16.s\n"
154 "ld1w { z16.s }, p0/Z, [x24, #-1, MUL VL]\n"
155 "st1h { z0.h }, p7, [x20]\n"
156 ".inst 0x648abe11 // bfcvtnt z17.h, p7/M, z16.s\n"
157 "st1h { z31.h }, p7, [x20, #1, MUL VL]\n"
158 "st1h { z30.h }, p7, [x20, #2, MUL VL]\n"
159 "st1h { z29.h }, p7, [x20, #3, MUL VL]\n"
160 "st1h { z28.h }, p7, [x20, #4, MUL VL]\n"
161 "st1h { z27.h }, p7, [x20, #5, MUL VL]\n"
162 "st1h { z26.h }, p7, [x20, #6, MUL VL]\n"
163 "st1h { z25.h }, p7, [x20, #7, MUL VL]\n"
164 "addvl x20, x20, #16\n"
165 "st1h { z24.h }, p7, [x20, #-8, MUL VL]\n"
166 "st1h { z23.h }, p7, [x20, #-7, MUL VL]\n"
167 "st1h { z22.h }, p7, [x20, #-6, MUL VL]\n"
168 "st1h { z21.h }, p7, [x20, #-5, MUL VL]\n"
169 "st1h { z20.h }, p7, [x20, #-4, MUL VL]\n"
170 "st1h { z19.h }, p7, [x20, #-3, MUL VL]\n"
171 "st1h { z18.h }, p7, [x20, #-2, MUL VL]\n"
172 "st1h { z17.h }, p7, [x20, #-1, MUL VL]\n"
175 "cmp %x[height], #0x1\n"
176 "addvl %x[out], %x[out], #16\n"
178 ".inst 0xd503467f // SMSTOP\n"
179 : [height]
"+&r" (height), [in]
"+&r" (in), [out]
"+&r" (out)
180 : [in_stride]
"r" (in_stride), [out_stride]
"r" (out_stride), [pad_row]
"r" (pad_row), [width]
"r" (width)
181 :
"cc",
"memory",
"p0",
"p1",
"p2",
"p3",
"p4",
"p5",
"p6",
"p7",
"p8",
"p9",
"p10",
"p11",
"p12",
"p13",
"p14",
"p15",
"x20",
"x21",
"x22",
"x23",
"x24",
"x25",
"z0",
"z1",
"z2",
"z3",
"z4",
"z5",
"z6",
"z7",
"z8",
"z9",
"z10",
"z11",
"z12",
"z13",
"z14",
"z15",
"z16",
"z17",
"z18",
"z19",
"z20",
"z21",
"z22",
"z23",
"z24",
"z25",
"z26",
"z27",
"z28",
"z29",
"z30",
"z31"
187 void Transform<16, 2, true, VLType::SME>(
188 bfloat16 *out,
const float *in,
int stride,
int x0,
int xmax,
int k0,
int kmax)
190 sme_transpose_interleave_16VL_2x2_fp32bf16(
192 in + k0 * stride + x0,
194 stride *
sizeof(
float),
200 #endif // defined(ARM_COMPUTE_ENABLE_SME)