27 #if defined(ARM_COMPUTE_ENABLE_SME)
31 void sme_transpose_interleave_1VL_2x2(uint16_t *out,
const uint16_t *in,
size_t width,
size_t in_stride,
size_t height)
33 uint16_t *pad_row =
reinterpret_cast<uint16_t *
>(alloca(width *
sizeof(uint16_t)));
36 memset(pad_row, 0, width *
sizeof(uint16_t));
39 size_t out_stride = 1 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>();
42 ".inst 0xd503477f // SMSTART ZA\n"
43 "cmp %x[height], #0x4\n"
48 "add x25, x26, %x[in_stride]\n"
49 "add x24, x25, %x[in_stride]\n"
50 "mov x23, %x[width]\n"
51 "cnth x21, ALL, MUL #2\n"
52 "add x20, x24, %x[in_stride]\n"
54 "add %x[in], x20, %x[in_stride]\n"
56 "sub %x[height], %x[height], #0x4\n"
59 "ld1h { z17.h }, p1/Z, [x26]\n"
62 "ld1h { z16.h }, p1/Z, [x25]\n"
63 "zip1 z24.h, z17.h, z16.h\n"
64 "zip2 z23.h, z17.h, z16.h\n"
65 "ld1h { z17.h }, p1/Z, [x24]\n"
66 "ld1h { z16.h }, p1/Z, [x20]\n"
67 "zip1 z22.h, z17.h, z16.h\n"
68 "zip2 z21.h, z17.h, z16.h\n"
69 "ld1h { z17.h }, p1/Z, [x26, #1, MUL VL]\n"
70 "addvl x26, x26, #2\n"
71 "ld1h { z16.h }, p1/Z, [x25, #1, MUL VL]\n"
72 "zip1 z20.h, z17.h, z16.h\n"
73 "addvl x25, x25, #2\n"
74 "zip2 z19.h, z17.h, z16.h\n"
75 "ld1h { z18.h }, p1/Z, [x24, #1, MUL VL]\n"
76 "addvl x24, x24, #2\n"
77 "ld1h { z16.h }, p1/Z, [x20, #1, MUL VL]\n"
78 "st1h { z24.h }, p1, [x22]\n"
79 "zip1 z17.h, z18.h, z16.h\n"
80 "addvl x20, x20, #2\n"
81 "st1h { z22.h }, p1, [x22, #1, MUL VL]\n"
82 "add x22, x22, %x[out_stride]\n"
83 "zip2 z16.h, z18.h, z16.h\n"
84 "st1h { z23.h }, p1, [x22]\n"
85 "st1h { z21.h }, p1, [x22, #1, MUL VL]\n"
86 "add x22, x22, %x[out_stride]\n"
87 "st1h { z20.h }, p1, [x22]\n"
88 "st1h { z17.h }, p1, [x22, #1, MUL VL]\n"
89 "add x22, x22, %x[out_stride]\n"
90 "st1h { z19.h }, p1, [x22]\n"
91 "st1h { z16.h }, p1, [x22, #1, MUL VL]\n"
92 "add x22, x22, %x[out_stride]\n"
97 "whilelt p0.h, XZR, x23\n"
98 "ld1h { z17.h }, p0/Z, [x26]\n"
100 "ld1h { z16.h }, p0/Z, [x25]\n"
102 "incd x26, ALL, MUL #4\n"
103 "zip1 z18.h, z17.h, z16.h\n"
104 "ld1h { z17.h }, p0/Z, [x24]\n"
105 "incd x25, ALL, MUL #4\n"
106 "incd x24, ALL, MUL #4\n"
107 "ld1h { z16.h }, p0/Z, [x20]\n"
108 "incd x20, ALL, MUL #4\n"
109 "zip1 z16.h, z17.h, z16.h\n"
110 "st1h { z18.h }, p1, [x22]\n"
111 "st1h { z16.h }, p1, [x22, #1, MUL VL]\n"
112 "add x22, x22, %x[out_stride]\n"
115 "cmp %x[height], #0x4\n"
116 "addvl %x[out], %x[out], #2\n"
118 "cbz %x[height], 12f\n"
122 "add x25, x26, %x[in_stride]\n"
123 "cmp %x[height], #0x1\n"
124 "mov x21, %x[width]\n"
125 "cnth x20, ALL, MUL #2\n"
126 "add %x[in], x25, %x[in_stride]\n"
127 "csel x25, x25, %x[pad_row], GT\n"
130 "sub %x[height], %x[height], #0x2\n"
133 "ld1h { z18.h }, p1/Z, [x26]\n"
134 "sub x21, x21, x20\n"
136 "ld1h { z16.h }, p1/Z, [x25]\n"
137 "zip1 z17.h, z18.h, z16.h\n"
138 "zip2 z19.h, z18.h, z16.h\n"
139 "ld1h { z18.h }, p1/Z, [x26, #1, MUL VL]\n"
140 "addvl x26, x26, #2\n"
141 "ld1h { z16.h }, p1/Z, [x25, #1, MUL VL]\n"
142 "st1h { z17.h }, p1, [x22]\n"
143 "add x22, x22, %x[out_stride]\n"
144 "zip1 z17.h, z18.h, z16.h\n"
145 "st1h { z19.h }, p1, [x22]\n"
146 "add x22, x22, %x[out_stride]\n"
147 "addvl x25, x25, #2\n"
148 "zip2 z16.h, z18.h, z16.h\n"
149 "st1h { z17.h }, p1, [x22]\n"
150 "add x22, x22, %x[out_stride]\n"
151 "st1h { z16.h }, p1, [x22]\n"
152 "add x22, x22, %x[out_stride]\n"
157 "whilelt p0.h, XZR, x21\n"
158 "ld1h { z17.h }, p0/Z, [x26]\n"
160 "ld1h { z16.h }, p0/Z, [x25]\n"
162 "incd x26, ALL, MUL #4\n"
163 "zip1 z16.h, z17.h, z16.h\n"
164 "incd x25, ALL, MUL #4\n"
165 "st1h { z16.h }, p1, [x22]\n"
166 "add x22, x22, %x[out_stride]\n"
169 "cmp %x[height], #0x1\n"
170 "addvl %x[out], %x[out], #1\n"
173 ".inst 0xd503467f // SMSTOP\n"
174 : [height]
"+&r" (height), [in]
"+&r" (in), [out]
"+&r" (out)
175 : [in_stride]
"r" (in_stride), [out_stride]
"r" (out_stride), [pad_row]
"r" (pad_row), [width]
"r" (width)
176 :
"cc",
"memory",
"p0",
"p1",
"p2",
"p3",
"p4",
"p5",
"p6",
"p7",
"p8",
"p9",
"p10",
"p11",
"p12",
"p13",
"p14",
"p15",
"x20",
"x21",
"x22",
"x23",
"x24",
"x25",
"x26",
"z0",
"z1",
"z2",
"z3",
"z4",
"z5",
"z6",
"z7",
"z8",
"z9",
"z10",
"z11",
"z12",
"z13",
"z14",
"z15",
"z16",
"z17",
"z18",
"z19",
"z20",
"z21",
"z22",
"z23",
"z24",
"z25",
"z26",
"z27",
"z28",
"z29",
"z30",
"z31"
183 void Transform<1, 2, true, VLType::SME>(
184 bfloat16 *out,
const bfloat16 *in,
int stride,
int x0,
int xmax,
int k0,
int kmax)
186 sme_transpose_interleave_1VL_2x2(
187 reinterpret_cast<uint16_t *
>(out),
188 reinterpret_cast<const uint16_t *
>(in + k0 * stride + x0),
196 void Transform<1, 2, true, VLType::SME>(
197 __fp16 *out,
const __fp16 *in,
int stride,
int x0,
int xmax,
int k0,
int kmax)
199 sme_transpose_interleave_1VL_2x2(
200 reinterpret_cast<uint16_t *
>(out),
201 reinterpret_cast<const uint16_t *
>(in + k0 * stride + x0),
202 (xmax-x0) *
sizeof(__fp16) / 2,
203 stride *
sizeof(__fp16),
208 #endif // defined(ARM_COMPUTE_ENABLE_SME)