27 #if defined(ARM_COMPUTE_ENABLE_SME)
31 void sme_transpose_interleave_8VL_2x2(uint16_t *out,
const uint16_t *in,
size_t width,
size_t in_stride,
size_t height)
33 uint16_t *pad_row =
reinterpret_cast<uint16_t *
>(alloca(width *
sizeof(uint16_t)));
36 memset(pad_row, 0, width *
sizeof(uint16_t));
39 size_t out_stride = 8 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>();
42 ".inst 0xd503477f // SMSTART ZA\n"
46 "add x23, x24, %x[in_stride]\n"
47 "cmp %x[height], #0x1\n"
48 "add %x[in], x23, %x[in_stride]\n"
50 "csel x23, x23, %x[pad_row], GT\n"
51 "sub %x[height], %x[height], #0x2\n"
52 "mov x21, %x[width]\n"
55 "whilelt p3.h, XZR, x20\n"
56 "ld1h { z20.h }, p3/Z, [x24]\n"
58 "whilelt p2.h, XZR, x20\n"
59 "ld1h { z19.h }, p2/Z, [x24, #1, MUL VL]\n"
61 "whilelt p1.h, XZR, x20\n"
62 "ld1h { z18.h }, p1/Z, [x24, #2, MUL VL]\n"
64 "whilelt p0.h, XZR, x20\n"
65 "ld1h { z24.h }, p0/Z, [x24, #3, MUL VL]\n"
66 "ld1h { z17.h }, p3/Z, [x23]\n"
67 "decw x21, ALL, MUL #8\n"
69 "zip1 z23.h, z20.h, z17.h\n"
70 "ld1h { z16.h }, p2/Z, [x23, #1, MUL VL]\n"
71 "addvl x24, x24, #4\n"
72 "zip2 z22.h, z20.h, z17.h\n"
73 "zip1 z21.h, z19.h, z16.h\n"
74 "ld1h { z17.h }, p1/Z, [x23, #2, MUL VL]\n"
75 "zip2 z20.h, z19.h, z16.h\n"
76 "zip1 z19.h, z18.h, z17.h\n"
77 "ld1h { z16.h }, p0/Z, [x23, #3, MUL VL]\n"
78 "addvl x23, x23, #4\n"
79 "zip2 z18.h, z18.h, z17.h\n"
80 "zip1 z17.h, z24.h, z16.h\n"
81 "zip2 z16.h, z24.h, z16.h\n"
82 "st1h { z23.h }, p4, [x22]\n"
83 "st1h { z22.h }, p4, [x22, #1, MUL VL]\n"
84 "st1h { z21.h }, p4, [x22, #2, MUL VL]\n"
85 "st1h { z20.h }, p4, [x22, #3, MUL VL]\n"
86 "st1h { z19.h }, p4, [x22, #4, MUL VL]\n"
87 "st1h { z18.h }, p4, [x22, #5, MUL VL]\n"
88 "st1h { z17.h }, p4, [x22, #6, MUL VL]\n"
89 "st1h { z16.h }, p4, [x22, #7, MUL VL]\n"
90 "add x22, x22, %x[out_stride]\n"
93 "cmp %x[height], #0x1\n"
94 "addvl %x[out], %x[out], #8\n"
96 ".inst 0xd503467f // SMSTOP\n"
97 : [height]
"+&r" (height), [in]
"+&r" (in), [out]
"+&r" (out)
98 : [in_stride]
"r" (in_stride), [out_stride]
"r" (out_stride), [pad_row]
"r" (pad_row), [width]
"r" (width)
99 :
"cc",
"memory",
"p0",
"p1",
"p2",
"p3",
"p4",
"p5",
"p6",
"p7",
"p8",
"p9",
"p10",
"p11",
"p12",
"p13",
"p14",
"p15",
"x20",
"x21",
"x22",
"x23",
"x24",
"z0",
"z1",
"z2",
"z3",
"z4",
"z5",
"z6",
"z7",
"z8",
"z9",
"z10",
"z11",
"z12",
"z13",
"z14",
"z15",
"z16",
"z17",
"z18",
"z19",
"z20",
"z21",
"z22",
"z23",
"z24",
"z25",
"z26",
"z27",
"z28",
"z29",
"z30",
"z31"
106 void Transform<8, 2, true, VLType::SME>(
107 bfloat16 *out,
const bfloat16 *in,
int stride,
int x0,
int xmax,
int k0,
int kmax)
109 sme_transpose_interleave_8VL_2x2(
110 reinterpret_cast<uint16_t *
>(out),
111 reinterpret_cast<const uint16_t *
>(in + k0 * stride + x0),
119 void Transform<8, 2, true, VLType::SME>(
120 __fp16 *out,
const __fp16 *in,
int stride,
int x0,
int xmax,
int k0,
int kmax)
122 sme_transpose_interleave_8VL_2x2(
123 reinterpret_cast<uint16_t *
>(out),
124 reinterpret_cast<const uint16_t *
>(in + k0 * stride + x0),
125 (xmax-x0) *
sizeof(__fp16) / 2,
126 stride *
sizeof(__fp16),
132 #endif // defined(ARM_COMPUTE_ENABLE_SME)