24.04
a64fx.cpp
Go to the documentation of this file.
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/*
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* Copyright (c) 2021, 2023 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifdef ARM_COMPUTE_ENABLE_SVE
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#include <cstddef>
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namespace
arm_gemm
{
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void
sve_interleaved_fp32_mla_8x3VL_a64fx(
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const
float
*Apanel,
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const
float
*Bpanel,
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float
*Cpanel,
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int
ablocks,
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int
bblocks,
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int
K
) {
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struct
KernelArgs {
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size_t
K
= {};
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const
float
*Bpanel = {};
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size_t
bblocks = {};
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} ka;
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ka.K = (
K
/1) - 1;
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ka.Bpanel = Bpanel;
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ka.bblocks = bblocks;
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__asm__ __volatile__(
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"ptrue p0.b\n"
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"1:"
// Height loop
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"ldr x23, [%x[args_ptr], %[offsetof_bblocks]]\n"
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"ldr x22, [%x[args_ptr], %[offsetof_Bpanel]]\n"
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"mov x21, %x[Apanel]\n"
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"2:"
// Width loop
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"ldr x20, [%x[args_ptr], %[offsetof_K]]\n"
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"mov %x[Apanel], x21\n"
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"cmp x20, #0x2\n"
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"mov z8.b, #0x0\n"
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"mov z9.b, #0x0\n"
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"ld1w { z0.s }, p0/Z, [x22]\n"
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"mov z10.b, #0x0\n"
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"mov z11.b, #0x0\n"
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"ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n"
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"mov z12.b, #0x0\n"
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"mov z13.b, #0x0\n"
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"ld1w { z2.s }, p0/Z, [x22, #2, MUL VL]\n"
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"mov z14.b, #0x0\n"
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"mov z15.b, #0x0\n"
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"ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n"
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"mov z16.b, #0x0\n"
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"mov z17.b, #0x0\n"
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"ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n"
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"mov z18.b, #0x0\n"
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"mov z19.b, #0x0\n"
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"ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n"
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"mov z20.b, #0x0\n"
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"mov z21.b, #0x0\n"
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"ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n"
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"mov z22.b, #0x0\n"
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"mov z23.b, #0x0\n"
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"mov z24.b, #0x0\n"
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"mov z25.b, #0x0\n"
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"mov z26.b, #0x0\n"
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"mov z27.b, #0x0\n"
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"mov z28.b, #0x0\n"
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"mov z29.b, #0x0\n"
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"mov z30.b, #0x0\n"
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"mov z31.b, #0x0\n"
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"blt 4f\n"
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"3:"
// main loop head
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"fmla z8.s, p0/M, z0.s, z3.s\n"
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"fmla z9.s, p0/M, z1.s, z3.s\n"
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"sub x20, x20, #0x2\n"
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"fmla z10.s, p0/M, z2.s, z3.s\n"
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"ld1rw { z7.s }, p0/Z, [%x[Apanel], #16]\n"
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"fmla z11.s, p0/M, z0.s, z4.s\n"
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"fmla z12.s, p0/M, z1.s, z4.s\n"
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"fmla z13.s, p0/M, z2.s, z4.s\n"
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"ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n"
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"fmla z14.s, p0/M, z0.s, z5.s\n"
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"fmla z15.s, p0/M, z1.s, z5.s\n"
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"cmp x20, #0x2\n"
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"fmla z16.s, p0/M, z2.s, z5.s\n"
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"ld1rw { z3.s }, p0/Z, [%x[Apanel], #24]\n"
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"fmla z17.s, p0/M, z0.s, z6.s\n"
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"fmla z18.s, p0/M, z1.s, z6.s\n"
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"fmla z19.s, p0/M, z2.s, z6.s\n"
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"ld1rw { z5.s }, p0/Z, [%x[Apanel], #28]\n"
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"fmla z20.s, p0/M, z0.s, z7.s\n"
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"fmla z21.s, p0/M, z1.s, z7.s\n"
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"fmla z22.s, p0/M, z2.s, z7.s\n"
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"ld1rw { z7.s }, p0/Z, [%x[Apanel], #32]\n"
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"fmla z23.s, p0/M, z0.s, z4.s\n"
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"fmla z24.s, p0/M, z1.s, z4.s\n"
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"fmla z25.s, p0/M, z2.s, z4.s\n"
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"ld1rw { z4.s }, p0/Z, [%x[Apanel], #36]\n"
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"fmla z26.s, p0/M, z0.s, z3.s\n"
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"fmla z27.s, p0/M, z1.s, z3.s\n"
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"fmla z28.s, p0/M, z2.s, z3.s\n"
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"ld1rw { z3.s }, p0/Z, [%x[Apanel], #40]\n"
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"fmla z29.s, p0/M, z0.s, z5.s\n"
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"ld1w { z6.s }, p0/Z, [x22, #3, MUL VL]\n"
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"fmla z30.s, p0/M, z1.s, z5.s\n"
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"fmla z31.s, p0/M, z2.s, z5.s\n"
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"ld1w { z2.s }, p0/Z, [x22, #4, MUL VL]\n"
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"ld1w { z5.s }, p0/Z, [x22, #5, MUL VL]\n"
127
"fmla z8.s, p0/M, z6.s, z7.s\n"
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"ld1rw { z1.s }, p0/Z, [%x[Apanel], #44]\n"
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"fmla z9.s, p0/M, z2.s, z7.s\n"
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"fmla z10.s, p0/M, z5.s, z7.s\n"
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"fmla z11.s, p0/M, z6.s, z4.s\n"
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"ld1rw { z7.s }, p0/Z, [%x[Apanel], #48]\n"
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"fmla z12.s, p0/M, z2.s, z4.s\n"
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"fmla z13.s, p0/M, z5.s, z4.s\n"
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"ld1rw { z4.s }, p0/Z, [%x[Apanel], #52]\n"
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"fmla z14.s, p0/M, z6.s, z3.s\n"
137
"fmla z15.s, p0/M, z2.s, z3.s\n"
138
"addvl x22, x22, #6\n"
139
"fmla z16.s, p0/M, z5.s, z3.s\n"
140
"ld1rw { z0.s }, p0/Z, [%x[Apanel], #56]\n"
141
"fmla z17.s, p0/M, z6.s, z1.s\n"
142
"fmla z18.s, p0/M, z2.s, z1.s\n"
143
"fmla z19.s, p0/M, z5.s, z1.s\n"
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"ld1rw { z1.s }, p0/Z, [%x[Apanel], #60]\n"
145
"add %x[Apanel], %x[Apanel], #0x40\n"
146
"fmla z20.s, p0/M, z6.s, z7.s\n"
147
"fmla z21.s, p0/M, z2.s, z7.s\n"
148
"fmla z22.s, p0/M, z5.s, z7.s\n"
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"fmla z23.s, p0/M, z6.s, z4.s\n"
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"ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n"
151
"fmla z24.s, p0/M, z2.s, z4.s\n"
152
"fmla z25.s, p0/M, z5.s, z4.s\n"
153
"ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n"
154
"fmla z26.s, p0/M, z6.s, z0.s\n"
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"fmla z27.s, p0/M, z2.s, z0.s\n"
156
"fmla z28.s, p0/M, z5.s, z0.s\n"
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"fmla z29.s, p0/M, z6.s, z1.s\n"
158
"ld1w { z0.s }, p0/Z, [x22]\n"
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"fmla z30.s, p0/M, z2.s, z1.s\n"
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"fmla z31.s, p0/M, z5.s, z1.s\n"
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"ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n"
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"ld1w { z2.s }, p0/Z, [x22, #2, MUL VL]\n"
163
"ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n"
164
"ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n"
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"bge 3b\n"
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"4:"
// main loop skip
167
"fmla z8.s, p0/M, z0.s, z3.s\n"
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"fmla z9.s, p0/M, z1.s, z3.s\n"
169
"addvl x22, x22, #3\n"
170
"fmla z10.s, p0/M, z2.s, z3.s\n"
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"ld1rw { z7.s }, p0/Z, [%x[Apanel], #16]\n"
172
"fmla z11.s, p0/M, z0.s, z4.s\n"
173
"fmla z12.s, p0/M, z1.s, z4.s\n"
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"fmla z13.s, p0/M, z2.s, z4.s\n"
175
"ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n"
176
"fmla z14.s, p0/M, z0.s, z5.s\n"
177
"fmla z15.s, p0/M, z1.s, z5.s\n"
178
"fmla z16.s, p0/M, z2.s, z5.s\n"
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"ld1rw { z5.s }, p0/Z, [%x[Apanel], #24]\n"
180
"fmla z17.s, p0/M, z0.s, z6.s\n"
181
"fmla z18.s, p0/M, z1.s, z6.s\n"
182
"fmla z19.s, p0/M, z2.s, z6.s\n"
183
"ld1rw { z3.s }, p0/Z, [%x[Apanel], #28]\n"
184
"fmla z20.s, p0/M, z0.s, z7.s\n"
185
"fmla z21.s, p0/M, z1.s, z7.s\n"
186
"add %x[Apanel], %x[Apanel], #0x20\n"
187
"fmla z22.s, p0/M, z2.s, z7.s\n"
188
"fmla z23.s, p0/M, z0.s, z4.s\n"
189
"fmla z24.s, p0/M, z1.s, z4.s\n"
190
"fmla z25.s, p0/M, z2.s, z4.s\n"
191
"fmla z26.s, p0/M, z0.s, z5.s\n"
192
"fmla z27.s, p0/M, z1.s, z5.s\n"
193
"fmla z28.s, p0/M, z2.s, z5.s\n"
194
"fmla z29.s, p0/M, z0.s, z3.s\n"
195
"fmla z30.s, p0/M, z1.s, z3.s\n"
196
"fmla z31.s, p0/M, z2.s, z3.s\n"
197
"cbz x20, 5f\n"
198
"ld1w { z6.s }, p0/Z, [x22]\n"
199
"ld1w { z5.s }, p0/Z, [x22, #1, MUL VL]\n"
200
"ld1w { z4.s }, p0/Z, [x22, #2, MUL VL]\n"
201
"ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n"
202
"fmla z8.s, p0/M, z6.s, z3.s\n"
203
"ld1rw { z2.s }, p0/Z, [%x[Apanel], #4]\n"
204
"ld1rw { z1.s }, p0/Z, [%x[Apanel], #8]\n"
205
"fmla z9.s, p0/M, z5.s, z3.s\n"
206
"ld1rw { z0.s }, p0/Z, [%x[Apanel], #12]\n"
207
"fmla z10.s, p0/M, z4.s, z3.s\n"
208
"fmla z11.s, p0/M, z6.s, z2.s\n"
209
"fmla z12.s, p0/M, z5.s, z2.s\n"
210
"fmla z13.s, p0/M, z4.s, z2.s\n"
211
"ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n"
212
"fmla z14.s, p0/M, z6.s, z1.s\n"
213
"fmla z15.s, p0/M, z5.s, z1.s\n"
214
"ld1rw { z2.s }, p0/Z, [%x[Apanel], #20]\n"
215
"fmla z16.s, p0/M, z4.s, z1.s\n"
216
"fmla z17.s, p0/M, z6.s, z0.s\n"
217
"ld1rw { z1.s }, p0/Z, [%x[Apanel], #24]\n"
218
"fmla z18.s, p0/M, z5.s, z0.s\n"
219
"fmla z19.s, p0/M, z4.s, z0.s\n"
220
"ld1rw { z0.s }, p0/Z, [%x[Apanel], #28]\n"
221
"fmla z20.s, p0/M, z6.s, z3.s\n"
222
"fmla z21.s, p0/M, z5.s, z3.s\n"
223
"addvl x22, x22, #3\n"
224
"fmla z22.s, p0/M, z4.s, z3.s\n"
225
"fmla z23.s, p0/M, z6.s, z2.s\n"
226
"add %x[Apanel], %x[Apanel], #0x20\n"
227
"fmla z24.s, p0/M, z5.s, z2.s\n"
228
"fmla z25.s, p0/M, z4.s, z2.s\n"
229
"fmla z26.s, p0/M, z6.s, z1.s\n"
230
"fmla z27.s, p0/M, z5.s, z1.s\n"
231
"fmla z28.s, p0/M, z4.s, z1.s\n"
232
"fmla z29.s, p0/M, z6.s, z0.s\n"
233
"fmla z30.s, p0/M, z5.s, z0.s\n"
234
"fmla z31.s, p0/M, z4.s, z0.s\n"
235
"5:"
// multiply loop done
236
"st1w { z8.s }, p0, [%x[Cpanel]]\n"
237
"subs x23, x23, #0x1\n"
238
"st1w { z9.s }, p0, [%x[Cpanel], #1, MUL VL]\n"
239
"st1w { z10.s }, p0, [%x[Cpanel], #2, MUL VL]\n"
240
"st1w { z11.s }, p0, [%x[Cpanel], #3, MUL VL]\n"
241
"st1w { z12.s }, p0, [%x[Cpanel], #4, MUL VL]\n"
242
"st1w { z13.s }, p0, [%x[Cpanel], #5, MUL VL]\n"
243
"st1w { z14.s }, p0, [%x[Cpanel], #6, MUL VL]\n"
244
"st1w { z15.s }, p0, [%x[Cpanel], #7, MUL VL]\n"
245
"addvl %x[Cpanel], %x[Cpanel], #16\n"
246
"st1w { z16.s }, p0, [%x[Cpanel], #-8, MUL VL]\n"
247
"st1w { z17.s }, p0, [%x[Cpanel], #-7, MUL VL]\n"
248
"st1w { z18.s }, p0, [%x[Cpanel], #-6, MUL VL]\n"
249
"st1w { z19.s }, p0, [%x[Cpanel], #-5, MUL VL]\n"
250
"st1w { z20.s }, p0, [%x[Cpanel], #-4, MUL VL]\n"
251
"st1w { z21.s }, p0, [%x[Cpanel], #-3, MUL VL]\n"
252
"st1w { z22.s }, p0, [%x[Cpanel], #-2, MUL VL]\n"
253
"st1w { z23.s }, p0, [%x[Cpanel], #-1, MUL VL]\n"
254
"st1w { z24.s }, p0, [%x[Cpanel]]\n"
255
"st1w { z25.s }, p0, [%x[Cpanel], #1, MUL VL]\n"
256
"st1w { z26.s }, p0, [%x[Cpanel], #2, MUL VL]\n"
257
"st1w { z27.s }, p0, [%x[Cpanel], #3, MUL VL]\n"
258
"st1w { z28.s }, p0, [%x[Cpanel], #4, MUL VL]\n"
259
"st1w { z29.s }, p0, [%x[Cpanel], #5, MUL VL]\n"
260
"st1w { z30.s }, p0, [%x[Cpanel], #6, MUL VL]\n"
261
"st1w { z31.s }, p0, [%x[Cpanel], #7, MUL VL]\n"
262
"addvl %x[Cpanel], %x[Cpanel], #8\n"
263
"bgt 2b\n"
264
"subs %x[ablocks], %x[ablocks], #0x1\n"
265
"bne 1b\n"
266
: [Apanel]
"+&r"
(Apanel), [Cpanel]
"+&r"
(Cpanel), [ablocks]
"+&r"
(ablocks)
267
: [args_ptr]
"r"
(&ka), [offsetof_Bpanel]
"I"
(offsetof(KernelArgs, Bpanel)), [offsetof_K]
"I"
(offsetof(KernelArgs,
K
)), [offsetof_bblocks]
"I"
(offsetof(KernelArgs, bblocks))
268
:
"cc"
,
"memory"
,
"p0"
,
"x20"
,
"x21"
,
"x22"
,
"x23"
,
"z0"
,
"z1"
,
"z2"
,
"z3"
,
"z4"
,
"z5"
,
"z6"
,
"z7"
,
"z8"
,
"z9"
,
"z10"
,
"z11"
,
"z12"
,
"z13"
,
"z14"
,
"z15"
,
"z16"
,
"z17"
,
"z18"
,
"z19"
,
"z20"
,
"z21"
,
"z22"
,
"z23"
,
"z24"
,
"z25"
,
"z26"
,
"z27"
,
"z28"
,
"z29"
,
"z30"
,
"z31"
269
);
270
}
271
272
}
// namespace arm_gemm
273
#endif // ARM_COMPUTE_ENABLE_SVE
arm_gemm
Definition:
barrier.hpp:30
K
unsigned int K
Definition:
CpuGemmAssemblyDispatch.cpp:106
src
core
NEON
kernels
arm_gemm
kernels
sve_interleaved_fp32_mla_8x3VL
a64fx.cpp
Generated on Mon Apr 29 2024 10:53:56 for Compute Library by
1.8.17