Keil MCBSTM32F400 Evaluation Board

This single processor demo application shows how to do the MPU Protection. Using CMSIS-Zone, it generates:

• A header file that contains #defines to control the various linker scatter files (and might be used in other parts of the application).
• The MPU configuration table source and header files. These contain MPU register settings used during thread switching to update accessible memory regions.

The application itself shows how to isolate network stack threads from the user application.

Using the CMSIS-Zone project

• Import the project "Examples\MCBSTM32F400\Zone" into the CMSIS-Zone utility
• Open the MCBSTM32F400.azone file
• Generate the related output files

The MCBSTM32F400.azone file of that project has the following configuration settings:

• Project mode is set to Execution.
• Added the zones Net, Main, RTX, Blinky, Timer, Idle
• Created the memory regions CODE, RAM_SHARED, RAM_NET, RAM_MAIN, RAM_PRIVILEGED, RAM_EVR, RAM_BSD, RAM_LED, RAM_ADC, RAM_TIMER, and RAM_IDLE
• Selected various memory regions and peripherals for using in the different zones:
  

The zones use common Flash region for all the application code but different SRAM regions to segregate thread data. To generate the output, click on the Generate button in the Zone Editor tool bar. This creates the following files in the ftl_gen directory:

Template File	Generated File	Description
dump_fzone.txt.ftl	dump_fzone.txt	Contains the complete model
helper.ftlinc	N/A	Helper template file with FTL functions.
mem_layout.h.ftl	mem_layout.h	Header file that contains the memory region definitions, for example for the linker scatter file.
mputable.c.ftl	mputable.c	MPU Table data definition.
mputable.h.ftl	mputable.h	MPU Table data declaration.
scatter.sct.ftl	scatter.sct	Example scatter file for MPU protection.

These files can be used in any IDE to create the final application. In the following, the usage in Arm Keil MDK is described.

Using the MDK project

The example project can be loaded, built and debugged in µVision by performing the following steps:

1. Navigate to Examples/MCBSTM32F400/MDK
2. Open the project workspace Blinky_Net.uvprojx
3. Optional: Update the generated files by executing the copy_gen.bat script.
4. Run the build in MDK.

MDK project setup

The projects Blinky_Net use the files generated in CMSIS-Zone as follows:

File	Description
mem_layout.h	Input for the linker scatter files.
mputable.c	MPU Table data definition.
mputable.h	MPU Table data declaration.
scatter.sct	Initial template for scatter file.

scatter.sct

As explained previously, the #defines in mem_layout.h can be used to create generic scatter files that are easy to update once changes in the CMSIS-Zone project happen. Using the mem_layout.h file from CMSIS-Zone, the following scatter file is used in the Blinky_Net project, which is based on the generated scatter file template (scatter.sct):

#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
 
#include "mem_layout.h"
 
LR_CODE REGION_CODE_START REGION_CODE_SIZE {
  ER_CODE REGION_CODE_START REGION_CODE_SIZE {
     .o (RESET,+FIRST)
      (InRoot$$Sections)
    .ANY (+RO, +XO)
  }
  RW_RAM_PRIVILEGED REGION_RAM_PRIVILEGED_START REGION_RAM_PRIVILEGED_SIZE {
     Net_Config.o (.bss.os.*.cb)
    .ANY (+RW +ZI)
  }
  RW_RAM_SHARED REGION_RAM_SHARED_START REGION_RAM_SHARED_SIZE {
    system_stm32f4xx.o (.data.SystemCoreClock)
;   *.o (.data.shared)
     .o (.bss.shared)
  }
  RW_RAM_EVR REGION_RAM_EVR_START UNINIT REGION_RAM_EVR_SIZE {
    EventRecorder.o (+ZI)
  }
  RW_RAM_BSD REGION_RAM_BSD_START REGION_RAM_BSD_SIZE {
    bsd.o (+RW +ZI)
  }
  RW_RAM_NET REGION_RAM_NET_START REGION_RAM_NET_SIZE {
    *Net*.lib (+RW +ZI)
    Net_Config.o (.bss*)
    emac_stm32f4xx.o (+RW +ZI)
    phy_ksz8081rna.o (+RW +ZI)
    phy_st802rt1.o (+RW +ZI)
  }
  RW_RAM_TIMER REGION_RAM_TIMER_START REGION_RAM_TIMER_SIZE {
    timer.o (+RW +ZI)
     .o (.bss.os.thread.stack.rtx.timer)
  }
  RW_RAM_ADC REGION_RAM_ADC_START REGION_RAM_ADC_SIZE {
    adc.o (+RW +ZI)
    adc_mcbstm32f400.o (+RW +ZI)
  }
  RW_RAM_LED REGION_RAM_LED_START REGION_RAM_LED_SIZE {
    led.o (+RW +ZI)
  }
  RW_RAM_MAIN REGION_RAM_MAIN_START REGION_RAM_MAIN_SIZE {
    app.o (+RW +ZI)
  }
  RW_RAM_IDLE REGION_RAM_IDLE_START REGION_RAM_IDLE_SIZE {
    RTX_Config.o (+RW +ZI)
     .o (.bss.os.thread.stack.rtx.idle)
  }
}

The data segments of segregated software components have been allocated to distinct memory regions.