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CMSIS-Core (Cortex-M)
Version 5.5.0
CMSIS-Core support for Cortex-M processor-based devices
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CMSIS-Core (Cortex-M)
Version 5.5.0
CMSIS-Core support for Cortex-M processor-based devices
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The Startup File startup_<device>.s (deprecated) contains:
The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.
To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with IRQn_Type that defines all the IRQ numbers for each interrupt.
Example:
The following example shows the extension of the interrupt vector table for the LPC1100 device family.
An Arm Compiler V6 assembler startup_Device.S Template File for an Armv8-M processor like Cortex-M33 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.
/**************************************************************************//**
* @file startup_<Device>.S
* @brief CMSIS-Core(M) Device Startup File for
* Device <Device> (using Arm Compiler 6 with scatter file)
* @version V1.0.0
* @date 20. January 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
/* ToDo: Set .arch to the architecture according the used Cortex-Core */
.arch armv8-m.main
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
#endif
.section RESET
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
/* ToDo: Add Cortex exception vectors according the used Cortex-Core */
__Vectors:
.long __INITIAL_SP /* Initial Stack Pointer */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* -14 NMI Handler */
.long HardFault_Handler /* -13 Hard Fault Handler */
.long MemManage_Handler /* -12 MPU Fault Handler */
.long BusFault_Handler /* -11 Bus Fault Handler */
.long UsageFault_Handler /* -10 Usage Fault Handler */
.long SecureFault_Handler /* -9 Secure Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVCall Handler */
.long DebugMon_Handler /* -4 Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* ToDo: Add your device specific interrupt vectors */
/* Interrupts */
.long <DeviceInterrupt first>_Handler /* first Device Interrupt */
...
.long <DeviceInterrupt last>_Handler /* last Device Interrupt */
/* ToDo: calculate the empty space according the used Cortex-Core */
.space (x * 4) /* Interrupts x .. 480 are left out */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
.thumb
.section .text
.align 2
.thumb_func
.type Reset_Handler, %function
.globl Reset_Handler
.fnstart
Reset_Handler:
ldr r0, =__INITIAL_SP
msr psp, r0
ldr r0, =__STACK_LIMIT
msr msplim, r0
msr psplim, r0
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ldr r0, =__STACK_SEAL
ldr r1, =0xFEF5EDA5U
strd r1,r1,[r0,#0]
#endif
bl SystemInit
bl __main
.fnend
.size Reset_Handler, . - Reset_Handler
/* The default macro is not used for HardFault_Handler
* because this results in a poor debug illusion.
*/
.thumb_func
.type HardFault_Handler, %function
.weak HardFault_Handler
.fnstart
HardFault_Handler:
b .
.fnend
.size HardFault_Handler, . - HardFault_Handler
.thumb_func
.type Default_Handler, %function
.weak Default_Handler
.fnstart
Default_Handler:
b .
.fnend
.size Default_Handler, . - Default_Handler
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Set_Default_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* ToDo: Add Cortex exception handler according the used Cortex-Core */
/* Default exception/interrupt handler */
Set_Default_Handler NMI_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SecureFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
/* ToDo: Add your device specific interrupt handler */
Set_Default_Handler <DeviceInterrupt first>_Handler
...
Set_Default_Handler <DeviceInterrupt last>_Handler
.end