CMSIS-Core (Cortex-A)  Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
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Bit position and mask macros. More...

Macros

#define CPSR_N_Pos   31U
 CPSR: N Position. More...
 
#define CPSR_N_Msk   (1UL << CPSR_N_Pos)
 CPSR: N Mask. More...
 
#define CPSR_Z_Pos   30U
 CPSR: Z Position. More...
 
#define CPSR_Z_Msk   (1UL << CPSR_Z_Pos)
 CPSR: Z Mask. More...
 
#define CPSR_C_Pos   29U
 CPSR: C Position. More...
 
#define CPSR_C_Msk   (1UL << CPSR_C_Pos)
 CPSR: C Mask. More...
 
#define CPSR_V_Pos   28U
 CPSR: V Position. More...
 
#define CPSR_V_Msk   (1UL << CPSR_V_Pos)
 CPSR: V Mask. More...
 
#define CPSR_Q_Pos   27U
 CPSR: Q Position. More...
 
#define CPSR_Q_Msk   (1UL << CPSR_Q_Pos)
 CPSR: Q Mask. More...
 
#define CPSR_IT0_Pos   25U
 CPSR: IT0 Position. More...
 
#define CPSR_IT0_Msk   (3UL << CPSR_IT0_Pos)
 CPSR: IT0 Mask. More...
 
#define CPSR_J_Pos   24U
 CPSR: J Position. More...
 
#define CPSR_J_Msk   (1UL << CPSR_J_Pos)
 CPSR: J Mask. More...
 
#define CPSR_GE_Pos   16U
 CPSR: GE Position. More...
 
#define CPSR_GE_Msk   (0xFUL << CPSR_GE_Pos)
 CPSR: GE Mask. More...
 
#define CPSR_IT1_Pos   10U
 CPSR: IT1 Position. More...
 
#define CPSR_IT1_Msk   (0x3FUL << CPSR_IT1_Pos)
 CPSR: IT1 Mask. More...
 
#define CPSR_E_Pos   9U
 CPSR: E Position. More...
 
#define CPSR_E_Msk   (1UL << CPSR_E_Pos)
 CPSR: E Mask. More...
 
#define CPSR_A_Pos   8U
 CPSR: A Position. More...
 
#define CPSR_A_Msk   (1UL << CPSR_A_Pos)
 CPSR: A Mask. More...
 
#define CPSR_I_Pos   7U
 CPSR: I Position. More...
 
#define CPSR_I_Msk   (1UL << CPSR_I_Pos)
 CPSR: I Mask. More...
 
#define CPSR_F_Pos   6U
 CPSR: F Position. More...
 
#define CPSR_F_Msk   (1UL << CPSR_F_Pos)
 CPSR: F Mask. More...
 
#define CPSR_T_Pos   5U
 CPSR: T Position. More...
 
#define CPSR_T_Msk   (1UL << CPSR_T_Pos)
 CPSR: T Mask. More...
 
#define CPSR_M_Pos   0U
 CPSR: M Position. More...
 
#define CPSR_M_Msk   (0x1FUL << CPSR_M_Pos)
 CPSR: M Mask. More...
 

Description

Macro Definition Documentation

#define CPSR_A_Msk   (1UL << CPSR_A_Pos)
#define CPSR_A_Pos   8U
#define CPSR_C_Msk   (1UL << CPSR_C_Pos)
#define CPSR_C_Pos   29U
#define CPSR_E_Msk   (1UL << CPSR_E_Pos)
#define CPSR_E_Pos   9U
#define CPSR_F_Msk   (1UL << CPSR_F_Pos)
#define CPSR_F_Pos   6U
#define CPSR_GE_Msk   (0xFUL << CPSR_GE_Pos)
#define CPSR_GE_Pos   16U
#define CPSR_I_Msk   (1UL << CPSR_I_Pos)
#define CPSR_I_Pos   7U
#define CPSR_IT0_Msk   (3UL << CPSR_IT0_Pos)
#define CPSR_IT0_Pos   25U
#define CPSR_IT1_Msk   (0x3FUL << CPSR_IT1_Pos)
#define CPSR_IT1_Pos   10U
#define CPSR_J_Msk   (1UL << CPSR_J_Pos)
#define CPSR_J_Pos   24U
#define CPSR_M_Msk   (0x1FUL << CPSR_M_Pos)
#define CPSR_M_Pos   0U
#define CPSR_N_Msk   (1UL << CPSR_N_Pos)
#define CPSR_N_Pos   31U
#define CPSR_Q_Msk   (1UL << CPSR_Q_Pos)
#define CPSR_Q_Pos   27U
#define CPSR_T_Msk   (1UL << CPSR_T_Pos)
#define CPSR_T_Pos   5U
#define CPSR_V_Msk   (1UL << CPSR_V_Pos)
#define CPSR_V_Pos   28U
#define CPSR_Z_Msk   (1UL << CPSR_Z_Pos)
#define CPSR_Z_Pos   30U