CMSIS-Core (Cortex-A)
Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
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Bit position and mask macros. More...
Macros | |
#define | IFSR_ExT_Pos 12U |
IFSR: ExT Position. More... | |
#define | IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) |
IFSR: ExT Mask. More... | |
#define | IFSR_LPAE_Pos 9U |
IFSR: LPAE Position. More... | |
#define | IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) |
IFSR: LPAE Mask. More... | |
#define | IFSR_FS1_Pos 10U |
IFSR: FS1 Position. More... | |
#define | IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) |
IFSR: FS1 Mask. More... | |
#define | IFSR_FS0_Pos 0U |
IFSR: FS0 Position. More... | |
#define | IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) |
IFSR: FS0 Mask. More... | |
#define | IFSR_STATUS_Pos 0U |
IFSR: STATUS Position. More... | |
#define | IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) |
IFSR: STATUS Mask. More... | |
#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) |
#define IFSR_ExT_Pos 12U |
#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) |
#define IFSR_FS0_Pos 0U |
#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) |
#define IFSR_FS1_Pos 10U |
#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) |
#define IFSR_LPAE_Pos 9U |
#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) |
#define IFSR_STATUS_Pos 0U |