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CMSIS-Core (Cortex-A)
Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A)
Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
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Bit position and mask macros. More...
Macros | |
| #define | SCTLR_TE_Pos 30U |
| SCTLR: TE Position. More... | |
| #define | SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) |
| SCTLR: TE Mask. More... | |
| #define | SCTLR_AFE_Pos 29U |
| SCTLR: AFE Position. More... | |
| #define | SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) |
| SCTLR: AFE Mask. More... | |
| #define | SCTLR_TRE_Pos 28U |
| SCTLR: TRE Position. More... | |
| #define | SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) |
| SCTLR: TRE Mask. More... | |
| #define | SCTLR_NMFI_Pos 27U |
| SCTLR: NMFI Position. More... | |
| #define | SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) |
| SCTLR: NMFI Mask. More... | |
| #define | SCTLR_EE_Pos 25U |
| SCTLR: EE Position. More... | |
| #define | SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) |
| SCTLR: EE Mask. More... | |
| #define | SCTLR_VE_Pos 24U |
| SCTLR: VE Position. More... | |
| #define | SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) |
| SCTLR: VE Mask. More... | |
| #define | SCTLR_U_Pos 22U |
| SCTLR: U Position. More... | |
| #define | SCTLR_U_Msk (1UL << SCTLR_U_Pos) |
| SCTLR: U Mask. More... | |
| #define | SCTLR_FI_Pos 21U |
| SCTLR: FI Position. More... | |
| #define | SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) |
| SCTLR: FI Mask. More... | |
| #define | SCTLR_UWXN_Pos 20U |
| SCTLR: UWXN Position. More... | |
| #define | SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) |
| SCTLR: UWXN Mask. More... | |
| #define | SCTLR_WXN_Pos 19U |
| SCTLR: WXN Position. More... | |
| #define | SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) |
| SCTLR: WXN Mask. More... | |
| #define | SCTLR_HA_Pos 17U |
| SCTLR: HA Position. More... | |
| #define | SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) |
| SCTLR: HA Mask. More... | |
| #define | SCTLR_RR_Pos 14U |
| SCTLR: RR Position. More... | |
| #define | SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) |
| SCTLR: RR Mask. More... | |
| #define | SCTLR_V_Pos 13U |
| SCTLR: V Position. More... | |
| #define | SCTLR_V_Msk (1UL << SCTLR_V_Pos) |
| SCTLR: V Mask. More... | |
| #define | SCTLR_I_Pos 12U |
| SCTLR: I Position. More... | |
| #define | SCTLR_I_Msk (1UL << SCTLR_I_Pos) |
| SCTLR: I Mask. More... | |
| #define | SCTLR_Z_Pos 11U |
| SCTLR: Z Position. More... | |
| #define | SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) |
| SCTLR: Z Mask. More... | |
| #define | SCTLR_SW_Pos 10U |
| SCTLR: SW Position. More... | |
| #define | SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) |
| SCTLR: SW Mask. More... | |
| #define | SCTLR_B_Pos 7U |
| SCTLR: B Position. More... | |
| #define | SCTLR_B_Msk (1UL << SCTLR_B_Pos) |
| SCTLR: B Mask. More... | |
| #define | SCTLR_CP15BEN_Pos 5U |
| SCTLR: CP15BEN Position. More... | |
| #define | SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) |
| SCTLR: CP15BEN Mask. More... | |
| #define | SCTLR_C_Pos 2U |
| SCTLR: C Position. More... | |
| #define | SCTLR_C_Msk (1UL << SCTLR_C_Pos) |
| SCTLR: C Mask. More... | |
| #define | SCTLR_A_Pos 1U |
| SCTLR: A Position. More... | |
| #define | SCTLR_A_Msk (1UL << SCTLR_A_Pos) |
| SCTLR: A Mask. More... | |
| #define | SCTLR_M_Pos 0U |
| SCTLR: M Position. More... | |
| #define | SCTLR_M_Msk (1UL << SCTLR_M_Pos) |
| SCTLR: M Mask. More... | |
| #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) |
| #define SCTLR_A_Pos 1U |
| #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) |
| #define SCTLR_AFE_Pos 29U |
| #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) |
| #define SCTLR_B_Pos 7U |
| #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) |
| #define SCTLR_C_Pos 2U |
| #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) |
| #define SCTLR_CP15BEN_Pos 5U |
| #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) |
| #define SCTLR_EE_Pos 25U |
| #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) |
| #define SCTLR_FI_Pos 21U |
| #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) |
| #define SCTLR_HA_Pos 17U |
| #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) |
| #define SCTLR_I_Pos 12U |
| #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) |
| #define SCTLR_M_Pos 0U |
| #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) |
| #define SCTLR_NMFI_Pos 27U |
| #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) |
| #define SCTLR_RR_Pos 14U |
| #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) |
| #define SCTLR_SW_Pos 10U |
| #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) |
| #define SCTLR_TE_Pos 30U |
| #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) |
| #define SCTLR_TRE_Pos 28U |
| #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) |
| #define SCTLR_U_Pos 22U |
| #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) |
| #define SCTLR_UWXN_Pos 20U |
| #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) |
| #define SCTLR_V_Pos 13U |
| #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) |
| #define SCTLR_VE_Pos 24U |
| #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) |
| #define SCTLR_WXN_Pos 19U |
| #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) |
| #define SCTLR_Z_Pos 11U |
