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CMSIS-Driver
Version 2.8.0
Peripheral Interface for Middleware and Application Code
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CMSIS-Driver
Version 2.8.0
Peripheral Interface for Middleware and Application Code
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Data Structures | |
| struct | ARM_USART_STATUS |
| USART Status. More... | |
| struct | ARM_USART_MODEM_STATUS |
| USART Modem Status. More... | |
| struct | ARM_USART_CAPABILITIES |
| USART Device Driver Capabilities. More... | |
| struct | ARM_DRIVER_USART |
| Access structure of the USART Driver. More... | |
Macros | |
| #define | ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ |
| #define | _ARM_Driver_USART_(n) Driver_USART##n |
| #define | ARM_Driver_USART_(n) _ARM_Driver_USART_(n) |
| #define | ARM_USART_CONTROL_Pos 0 |
| #define | ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) |
| #define | ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) |
| UART (Asynchronous); arg = Baudrate. More... | |
| #define | ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) |
| Synchronous Master (generates clock signal); arg = Baudrate. More... | |
| #define | ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) |
| Synchronous Slave (external clock signal) More... | |
| #define | ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) |
| UART Single-wire (half-duplex); arg = Baudrate. More... | |
| #define | ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) |
| UART IrDA; arg = Baudrate. More... | |
| #define | ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) |
| UART Smart Card; arg = Baudrate. More... | |
| #define | ARM_USART_DATA_BITS_Pos 8 |
| #define | ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) |
| #define | ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) |
| 5 Data bits More... | |
| #define | ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) |
| 6 Data bit More... | |
| #define | ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) |
| 7 Data bits More... | |
| #define | ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) |
| 8 Data bits (default) More... | |
| #define | ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) |
| 9 Data bits More... | |
| #define | ARM_USART_PARITY_Pos 12 |
| #define | ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) |
| #define | ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) |
| No Parity (default) More... | |
| #define | ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) |
| Even Parity. More... | |
| #define | ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) |
| Odd Parity. More... | |
| #define | ARM_USART_STOP_BITS_Pos 14 |
| #define | ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) |
| #define | ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) |
| 1 Stop bit (default) More... | |
| #define | ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) |
| 2 Stop bits More... | |
| #define | ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) |
| 1.5 Stop bits More... | |
| #define | ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) |
| 0.5 Stop bits More... | |
| #define | ARM_USART_FLOW_CONTROL_Pos 16 |
| #define | ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) |
| #define | ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) |
| No Flow Control (default) More... | |
| #define | ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) |
| RTS Flow Control. More... | |
| #define | ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) |
| CTS Flow Control. More... | |
| #define | ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) |
| RTS/CTS Flow Control. More... | |
| #define | ARM_USART_CPOL_Pos 18 |
| #define | ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) |
| #define | ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) |
| CPOL = 0 (default) More... | |
| #define | ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) |
| CPOL = 1. More... | |
| #define | ARM_USART_CPHA_Pos 19 |
| #define | ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) |
| #define | ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) |
| CPHA = 0 (default) More... | |
| #define | ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) |
| CPHA = 1. More... | |
| #define | ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) |
| Set default Transmit value (Synchronous Receive only); arg = value. More... | |
| #define | ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) |
| Set IrDA Pulse in ns; arg: 0=3/16 of bit period. More... | |
| #define | ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) |
| Set Smart Card Guard Time; arg = number of bit periods. More... | |
| #define | ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) |
| Set Smart Card Clock in Hz; arg: 0=Clock not generated. More... | |
| #define | ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) |
| Smart Card NACK generation; arg: 0=disabled, 1=enabled. More... | |
| #define | ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) |
| Transmitter; arg: 0=disabled, 1=enabled. More... | |
| #define | ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) |
| Receiver; arg: 0=disabled, 1=enabled. More... | |
| #define | ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) |
| Continuous Break transmission; arg: 0=disabled, 1=enabled. More... | |
| #define | ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) |
| Abort ARM_USART_Send. More... | |
| #define | ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) |
| Abort ARM_USART_Receive. More... | |
| #define | ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) |
| Abort ARM_USART_Transfer. More... | |
| #define | ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) |
| Specified Mode not supported. More... | |
| #define | ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) |
| Specified baudrate not supported. More... | |
| #define | ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) |
| Specified number of Data bits not supported. More... | |
| #define | ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) |
| Specified Parity not supported. More... | |
| #define | ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) |
| Specified number of Stop bits not supported. More... | |
| #define | ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) |
| Specified Flow Control not supported. More... | |
| #define | ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) |
| Specified Clock Polarity not supported. More... | |
| #define | ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) |
| Specified Clock Phase not supported. More... | |
| #define | ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) |
| Send completed; however USART may still transmit data. More... | |
| #define | ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) |
| Receive completed. More... | |
| #define | ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) |
| Transfer completed. More... | |
| #define | ARM_USART_EVENT_TX_COMPLETE (1UL << 3) |
| Transmit completed (optional) More... | |
| #define | ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) |
| Transmit data not available (Synchronous Slave) More... | |
| #define | ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) |
| Receive data overflow. More... | |
| #define | ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) |
| Receive character timeout (optional) More... | |
| #define | ARM_USART_EVENT_RX_BREAK (1UL << 7) |
| Break detected on receive. More... | |
| #define | ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) |
| Framing error detected on receive. More... | |
| #define | ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) |
| Parity error detected on receive. More... | |
| #define | ARM_USART_EVENT_CTS (1UL << 10) |
| CTS state changed (optional) More... | |
| #define | ARM_USART_EVENT_DSR (1UL << 11) |
| DSR state changed (optional) More... | |
| #define | ARM_USART_EVENT_DCD (1UL << 12) |
| DCD state changed (optional) More... | |
| #define | ARM_USART_EVENT_RI (1UL << 13) |
| RI state changed (optional) More... | |
Typedefs | |
| typedef void(* | ARM_USART_SignalEvent_t )(uint32_t event) |
| Pointer to ARM_USART_SignalEvent : Signal USART Event. More... | |
Enumerations | |
| enum | ARM_USART_MODEM_CONTROL { ARM_USART_RTS_CLEAR, ARM_USART_RTS_SET, ARM_USART_DTR_CLEAR, ARM_USART_DTR_SET } |
| USART Modem Control. More... | |
| #define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ |
| #define _ARM_Driver_USART_ | ( | n | ) | Driver_USART##n |
| #define ARM_Driver_USART_ | ( | n | ) | _ARM_Driver_USART_(n) |
| #define ARM_USART_CONTROL_Pos 0 |
| #define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) |
| #define ARM_USART_DATA_BITS_Pos 8 |
| #define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) |
| #define ARM_USART_PARITY_Pos 12 |
| #define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) |
| #define ARM_USART_STOP_BITS_Pos 14 |
| #define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) |
| #define ARM_USART_FLOW_CONTROL_Pos 16 |
| #define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) |
| #define ARM_USART_CPOL_Pos 18 |
| #define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) |
| #define ARM_USART_CPHA_Pos 19 |
| #define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) |
