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#define | IRQ_CTRL_H_ |
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#define | IRQHANDLER_T |
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#define | IRQN_ID_T |
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#define | IRQ_MODE_TRIG_Pos (0U) |
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#define | IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) |
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#define | IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: level triggered interrupt. More...
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#define | IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: low level triggered interrupt. More...
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#define | IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: high level triggered interrupt. More...
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#define | IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: edge triggered interrupt. More...
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#define | IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: rising edge triggered interrupt. More...
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#define | IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: falling edge triggered interrupt. More...
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#define | IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: rising and falling edge triggered interrupt. More...
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#define | IRQ_MODE_TYPE_Pos (3U) |
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#define | IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) |
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#define | IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) |
| Type: interrupt source triggers CPU IRQ line. More...
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#define | IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) |
| Type: interrupt source triggers CPU FIQ line. More...
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#define | IRQ_MODE_DOMAIN_Pos (4U) |
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#define | IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) |
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#define | IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) |
| Domain: interrupt is targeting non-secure domain. More...
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#define | IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) |
| Domain: interrupt is targeting secure domain. More...
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#define | IRQ_MODE_CPU_Pos (5U) |
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#define | IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) |
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#define | IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets all CPUs. More...
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#define | IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 0. More...
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#define | IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 1. More...
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#define | IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 2. More...
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#define | IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 3. More...
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#define | IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 4. More...
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#define | IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 5. More...
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#define | IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 6. More...
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#define | IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 7. More...
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#define | IRQ_MODE_MODEL_Pos (13U) |
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#define | IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) |
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#define | IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) |
| Corresponding interrupt is handled using the N-N model. More...
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#define | IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) |
| Corresponding interrupt is handled using the 1-N model. More...
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#define | IRQ_MODE_ERROR (0x80000000UL) |
| Bit indicating mode value error. More...
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#define | IRQ_PRIORITY_Msk (0x0000FFFFUL) |
| Interrupt priority value bit-mask. More...
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#define | IRQ_PRIORITY_ERROR (0x80000000UL) |
| Bit indicating priority value error. More...
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