Structure type to access the Private Timer.

Data Fields
__IOM uint32_t	LOAD
	Offset: 0x000 (R/W) Private Timer Load Register. More...

__IOM uint32_t	COUNTER
	Offset: 0x004 (R/W) Private Timer Counter Register. More...

__IOM uint32_t	CONTROL
	Offset: 0x008 (R/W) Private Timer Control Register. More...

__IOM uint32_t	ISR
	Offset: 0x00C (R/W) Private Timer Interrupt Status Register. More...

__IOM uint32_t	WLOAD
	Offset: 0x020 (R/W) Watchdog Load Register. More...

__IOM uint32_t	WCOUNTER
	Offset: 0x024 (R/W) Watchdog Counter Register. More...

__IOM uint32_t	WCONTROL
	Offset: 0x028 (R/W) Watchdog Control Register. More...

__IOM uint32_t	WISR
	Offset: 0x02C (R/W) Watchdog Interrupt Status Register. More...

__IOM uint32_t	WRESET
	Offset: 0x030 (R/W) Watchdog Reset Status Register. More...

__OM uint32_t	WDISABLE
	Offset: 0x034 ( /W) Watchdog Disable Register. More...

Field Documentation

__IOM uint32_t Timer_Type::CONTROL

Private Timer Control Register

Bits	Name	Function
[31:16]	-	Reserved.
[15:8]	Prescaler	The prescaler modifies the clock period for the decrementing event for the Counter Register.
[7:3]	-	Reserved.
[2]	IRQ Enable	If set, the interrupt is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register.
[1]	Auto Reload	If set, each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register.
[0]	Time Enabled	If set, Timer is enabled and the counter decrements normally.

__IOM uint32_t Timer_Type::COUNTER

Private Timer Counter Register The Timer Counter Register is a decrementing counter.

The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register.

When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops.

When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register.

Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value.

__IM uint32_t Timer_Type::ISR

Private Timer Interrupt Status Register

The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1.

__IOM uint32_t Timer_Type::LOAD

Private Timer Load Register The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register.

__IOM uint32_t Timer_Type::WCONTROL

Watchdog Control Register

Bits	Name	Function
[31:16]	-	Reserved.
[15:8]	Prescaler	The prescaler modifies the clock period for the decrementing event for the Counter Register.
[7:4]	-	Reserved.
[3]	Watchdog Mode	0 - Timer mode (default), 1 - Watchdog mode
[2]	IT Enable	Interrupt enable for timer mode.
[1]	Auto Reload	0 - Single shot mode, 1 - Continuous timer mode
[0]	Watchdog Enable	0 - Watchdog counter disabled, 1 - Watchdog timer enabled

__IOM uint32_t Timer_Type::WCOUNTER

Watchdog Counter Register

The Watchdog Counter Register is a down counter.

The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its current mode:

Timer mode: The watchdog interrupt status event flag is set and the interrupt is set as pending in the Interrupt Distributor.
Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ reset request output pin is asserted.

__IM uint32_t Timer_Type::WDISABLE

Watchdog Disable Register

Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.

__IOM uint32_t Timer_Type::WISR

Watchdog Interrupt Status Register

Bits	Name	Function
[31:1]	-	Reserved.
[0]	Event Flag	The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode.

__IOM uint32_t Timer_Type::WLOAD

Watchdog Load Register

The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register.

__IOM uint32_t Timer_Type::WRESET

Watchdog Reset Status Register

Bits	Name	Function
[31:1]	-	Reserved.
[0]	Reset Flag	The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode)

Data Fields

Field Documentation