CMSIS-Core (Cortex-A)  Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
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ACTLR_Type Struct Reference

Bit field declaration for ACTLR layout.

Data Fields

struct {
   uint32_t   FW:1
 bit: 0 Cache and TLB maintenance broadcast More...
 
   uint32_t   SMP:1
 bit: 6 Enables coherent requests to the processor More...
 
   uint32_t   EXCL:1
 bit: 7 Exclusive L1/L2 cache control More...
 
   uint32_t   DODMBS:1
 bit: 10 Disable optimized data memory barrier behavior More...
 
   uint32_t   DWBST:1
 bit: 11 AXI data write bursts to Normal memory More...
 
   uint32_t   RADIS:1
 bit: 12 L1 Data Cache read-allocate mode disable More...
 
   uint32_t   L1PCTL:2
 bit:13..14 L1 Data prefetch control More...
 
   uint32_t   BP:2
 bit:16..15 Branch prediction policy More...
 
   uint32_t   RSDIS:1
 bit: 17 Disable return stack operation More...
 
   uint32_t   BTDIS:1
 bit: 18 Disable indirect Branch Target Address Cache (BTAC) More...
 
   uint32_t   DBDI:1
 bit: 28 Disable branch dual issue More...
 
b
 Structure used for bit access on Cortex-A5. More...
 
struct {
   uint32_t   SMP:1
 bit: 6 Enables coherent requests to the processor More...
 
   uint32_t   DODMBS:1
 bit: 10 Disable optimized data memory barrier behavior More...
 
   uint32_t   L2RADIS:1
 bit: 11 L2 Data Cache read-allocate mode disable More...
 
   uint32_t   L1RADIS:1
 bit: 12 L1 Data Cache read-allocate mode disable More...
 
   uint32_t   L1PCTL:2
 bit:13..14 L1 Data prefetch control More...
 
   uint32_t   DDVM:1
 bit: 15 Disable Distributed Virtual Memory (DVM) transactions More...
 
   uint32_t   DDI:1
 bit: 28 Disable dual issue More...
 
b
 Structure used for bit access on Cortex-A7. More...
 
struct {
   uint32_t   FW:1
 bit: 0 Cache and TLB maintenance broadcast More...
 
   uint32_t   L1PE:1
 bit: 2 Dside prefetch More...
 
   uint32_t   WFLZM:1
 bit: 3 Cache and TLB maintenance broadcast More...
 
   uint32_t   SMP:1
 bit: 6 Enables coherent requests to the processor More...
 
   uint32_t   EXCL:1
 bit: 7 Exclusive L1/L2 cache control More...
 
   uint32_t   AOW:1
 bit: 8 Enable allocation in one cache way only More...
 
   uint32_t   PARITY:1
 bit: 9 Support for parity checking, if implemented More...
 
b
 Structure used for bit access on Cortex-A9. More...
 
uint32_t w
 Type used for word access. More...
 

Field Documentation

uint32_t ACTLR_Type::AOW
struct { ... } ACTLR_Type::b
struct { ... } ACTLR_Type::b
struct { ... } ACTLR_Type::b
uint32_t ACTLR_Type::BP
uint32_t ACTLR_Type::BTDIS
uint32_t ACTLR_Type::DBDI
uint32_t ACTLR_Type::DDI
uint32_t ACTLR_Type::DDVM
uint32_t ACTLR_Type::DODMBS
uint32_t ACTLR_Type::DWBST
uint32_t ACTLR_Type::EXCL
uint32_t ACTLR_Type::FW
uint32_t ACTLR_Type::L1PCTL
uint32_t ACTLR_Type::L1PE
uint32_t ACTLR_Type::L1RADIS
uint32_t ACTLR_Type::L2RADIS
uint32_t ACTLR_Type::PARITY
uint32_t ACTLR_Type::RADIS
uint32_t ACTLR_Type::RSDIS
uint32_t ACTLR_Type::SMP
uint32_t ACTLR_Type::w
uint32_t ACTLR_Type::WFLZM