CMSIS-Driver
Version 2.8.0
Peripheral Interface for Middleware and Application Code
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Specify bus mode of the NAND interface. More...
Macros | |
#define | ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) |
Data Interface: SDR (Single Data Rate) - Traditional interface (default) More... | |
#define | ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) |
Data Interface: NV-DDR (Double Data Rate) More... | |
#define | ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) |
Data Interface: NV-DDR2 (Double Data Rate) More... | |
#define | ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 0 (default) More... | |
#define | ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 1. More... | |
#define | ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 2. More... | |
#define | ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 3. More... | |
#define | ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 4 (SDR EDO capable) More... | |
#define | ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 5 (SDR EDO capable) More... | |
#define | ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 6 (NV-DDR2 only) More... | |
#define | ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 7 (NV-DDR2 only) More... | |
#define | ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 0 (default) More... | |
#define | ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 1. More... | |
#define | ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 2. More... | |
#define | ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 4. More... | |
#define | ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 0 (default) More... | |
#define | ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 1. More... | |
#define | ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 2. More... | |
#define | ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 4. More... | |
#define | ARM_NAND_BUS_DDR2_VEN (1UL << 16) |
DDR2 Enable external VREFQ as reference. More... | |
#define | ARM_NAND_BUS_DDR2_CMPD (1UL << 17) |
DDR2 Enable complementary DQS (DQS_c) signal. More... | |
#define | ARM_NAND_BUS_DDR2_CMPR (1UL << 18) |
DDR2 Enable complementary RE_n (RE_c) signal. More... | |
Specify bus mode of the NAND interface.
The defines can be used in the function ARM_NAND_Control for the parameter arg and with the ARM_NAND_BUS_MODE as the control code.
#define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) |
Data Interface: SDR (Single Data Rate) - Traditional interface (default)
#define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) |
Data Interface: NV-DDR (Double Data Rate)
#define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) |
Data Interface: NV-DDR2 (Double Data Rate)
#define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 0 (default)
#define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 1.
#define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 2.
#define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 3.
#define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 4 (SDR EDO capable)
#define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 5 (SDR EDO capable)
#define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 6 (NV-DDR2 only)
#define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) |
Timing Mode 7 (NV-DDR2 only)
#define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 0 (default)
#define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 1.
#define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 2.
#define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) |
DDR2 Data Output Warm-up cycles: 4.
#define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 0 (default)
#define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 1.
#define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 2.
#define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) |
DDR2 Data Input Warm-up cycles: 4.
#define ARM_NAND_BUS_DDR2_VEN (1UL << 16) |
DDR2 Enable external VREFQ as reference.
#define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) |
DDR2 Enable complementary DQS (DQS_c) signal.
#define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) |
DDR2 Enable complementary RE_n (RE_c) signal.