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CMSIS-Driver
Version 2.8.0
Peripheral Interface for Middleware and Application Code
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CMSIS-Driver
Version 2.8.0
Peripheral Interface for Middleware and Application Code
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Specifies SPI slave select mode. More...
Macros | |
| #define | ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| SPI Slave Select when Master: Not used (default) More... | |
| #define | ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| SPI Slave Select when Master: Software controlled. More... | |
| #define | ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| SPI Slave Select when Master: Hardware controlled Output. More... | |
| #define | ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) |
| SPI Slave Select when Master: Hardware monitored Input. More... | |
| #define | ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) |
| SPI Slave Select when Slave: Hardware monitored (default) More... | |
| #define | ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) |
| SPI Slave Select when Slave: Software controlled. More... | |
Specifies SPI slave select mode.
SPI Slave Select Mode configures the behavior of the Slave Select (SS) signal. The configuration is separate for Master (ARM_SPI_SS_MASTER_*) and for Slave (ARM_SPI_SS_SLAVE_HW, ARM_SPI_SS_SLAVE_SW). The active configuration depends on the current state (Master/Slave).
| #define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) |
SPI Slave Select when Master: Not used (default)
An SPI master does not drive or monitor the SS line. For example, when connecting to a single slave, the SS line can be connected to a fixed low level.
| #define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) |
SPI Slave Select when Master: Software controlled.
SS is configured as an output and controlled via ARM_SPI_Control (ARM_SPI_CONTROL_SS). By default, it is not active (high). It is activated (low) by ARM_SPI_Control (ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE) and deactivated by ARM_SPI_Control (ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE). It is not affected by transfer/send/receive functions.
| #define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) |
SPI Slave Select when Master: Hardware controlled Output.
Here, SS is configured as an output. It will be automatically activated/deactivated for the transfers by hardware (not controlled by ARM_SPI_Control (ARM_SPI_CONTROL_SS)). The activation/deactivation of the line is completely hardware dependent. Typically, the hardware will activate it before starting a transfer and deactivate it after a transfer completes. Some hardware will keep the line active as long as the SPI stays master. Due to different hardware behavior, this mode is typically not useful because certain devices require that the SS signal is strictly defined with regards to transfers.
| #define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) |
SPI Slave Select when Master: Hardware monitored Input.
This is normally used in a multi-master configuration, where a master does not drive the SS line when driving the bus but only monitors it. When another master activates this line, the active master backs off. This is called mode fault. SS is configured as input and the hardware only monitors it. When it is externally deactivated while being the master, it presents a mode fault and the SPI switches to inactive mode.
| #define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) |
SPI Slave Select when Slave: Hardware monitored (default)
Hardware monitors the SS line and accepts transfers only when SS line is activate. Transfers while SS is not active are ignored.
| #define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) |
SPI Slave Select when Slave: Software controlled.
Used only when SS line is not used. For example, when a single master and slave are connected in a system, the SS line is not needed (reduces the number of lines and pins used). Slave responses are controlled by software (by default, it is not responding). Software enables/disables transfers by calling ARM_SPI_Control (ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE / ARM_SPI_SS_INACTIVE).
