CMSIS-Core (Cortex-M)  
CMSIS-Core support for Cortex-M processor-based devices
 
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DCB_Type Struct Reference

Structure type to access the Debug Control Block Registers (DCB). More...

Data Fields

__IOM uint32_t DAUTHCTRL
 Offset: 0x014 (R/W) Debug Authentication Control Register (Armv8-M only)
 
__IOM uint32_t DCRDR
 Offset: 0x008 (R/W) Debug Core Register Data Register.
 
__OM uint32_t DCRSR
 Offset: 0x004 ( /W) Debug Core Register Selector Register.
 
__IOM uint32_t DEMCR
 Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
 
__IOM uint32_t DHCSR
 Offset: 0x000 (R/W) Debug Halting Control and Status Register.
 
__OM uint32_t DSCEMCR
 Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register (Armv8.1-M only)
 
__IOM uint32_t DSCSR
 Offset: 0x018 (R/W) Debug Security Control and Status Register (Armv8-M only)
 

Description

Structure type to access the Debug Control Block Registers (DCB).

Field Documentation

◆ DAUTHCTRL

__IOM uint32_t DCB_Type::DAUTHCTRL

Offset: 0x014 (R/W) Debug Authentication Control Register (Armv8-M only)

◆ DCRDR

__IOM uint32_t DCB_Type::DCRDR

Offset: 0x008 (R/W) Debug Core Register Data Register.

◆ DCRSR

__OM uint32_t DCB_Type::DCRSR

Offset: 0x004 ( /W) Debug Core Register Selector Register.

◆ DEMCR

__IOM uint32_t DCB_Type::DEMCR

Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.

◆ DHCSR

__IOM uint32_t DCB_Type::DHCSR

Offset: 0x000 (R/W) Debug Halting Control and Status Register.

◆ DSCEMCR

__OM uint32_t DCB_Type::DSCEMCR

Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register (Armv8.1-M only)

◆ DSCSR

__IOM uint32_t DCB_Type::DSCSR

Offset: 0x018 (R/W) Debug Security Control and Status Register (Armv8-M only)