CMSIS-Core (Cortex-M)  
CMSIS-Core support for Cortex-M processor-based devices
 
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EWIC_Type Struct Reference

Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). More...

Data Fields

__IOM uint32_t EWIC_ASCR
 Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register.
 
__OM uint32_t EWIC_CLRMASK
 Offset: 0x008 ( /W) EWIC Clear Mask Register.
 
__IOM uint32_t EWIC_CR
 Offset: 0x000 (R/W) EWIC Control Register.
 
__IOM uint32_t EWIC_MASKA
 Offset: 0x200 (R/W) EWIC MaskA Register.
 
__IOM uint32_t EWIC_MASKn [15]
 Offset: 0x204 (R/W) EWIC Maskn Registers.
 
__IM uint32_t EWIC_NUMID
 Offset: 0x00C (R/ ) EWIC Event Number ID Register.
 
__IM uint32_t EWIC_PENDA
 Offset: 0x400 (R/ ) EWIC PendA Event Register.
 
__IOM uint32_t EWIC_PENDn [15]
 Offset: 0x404 (R/W) EWIC Pendn Event Registers.
 
__IM uint32_t EWIC_PSR
 Offset: 0x600 (R/ ) EWIC Pend Summary Register.
 

Description

Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).

Field Documentation

◆ EWIC_ASCR

__IOM uint32_t EWIC_Type::EWIC_ASCR

Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register.

◆ EWIC_CLRMASK

__OM uint32_t EWIC_Type::EWIC_CLRMASK

Offset: 0x008 ( /W) EWIC Clear Mask Register.

◆ EWIC_CR

__IOM uint32_t EWIC_Type::EWIC_CR

Offset: 0x000 (R/W) EWIC Control Register.

◆ EWIC_MASKA

__IOM uint32_t EWIC_Type::EWIC_MASKA

Offset: 0x200 (R/W) EWIC MaskA Register.

◆ EWIC_MASKn

__IOM uint32_t EWIC_Type::EWIC_MASKn[15]

Offset: 0x204 (R/W) EWIC Maskn Registers.

◆ EWIC_NUMID

__IM uint32_t EWIC_Type::EWIC_NUMID

Offset: 0x00C (R/ ) EWIC Event Number ID Register.

◆ EWIC_PENDA

__IM uint32_t EWIC_Type::EWIC_PENDA

Offset: 0x400 (R/ ) EWIC PendA Event Register.

◆ EWIC_PENDn

__IOM uint32_t EWIC_Type::EWIC_PENDn[15]

Offset: 0x404 (R/W) EWIC Pendn Event Registers.

◆ EWIC_PSR

__IM uint32_t EWIC_Type::EWIC_PSR

Offset: 0x600 (R/ ) EWIC Pend Summary Register.