CMSIS-Core (Cortex-M)  
CMSIS-Core support for Cortex-M processor-based devices
 
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ITM_Type Struct Reference

Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

Data Fields

__IM uint32_t DEVARCH
 
__IOM uint32_t IMCR
 
__IM uint32_t IRR
 
__OM uint32_t IWR
 
__OM uint32_t LAR
 
__IM uint32_t LSR
 
union {
   __OM uint16_t   u16
 
   __OM uint32_t   u32
 
   __OM uint8_t   u8
 
PORT [32U]
 
__IOM uint32_t TCR
 
__IOM uint32_t TER
 
__IOM uint32_t TPR
 

Description

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

Field Documentation

◆ DEVARCH

__IM uint32_t ITM_Type::DEVARCH

Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only)

◆ IMCR

__IOM uint32_t ITM_Type::IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

◆ IRR

__IM uint32_t ITM_Type::IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

◆ IWR

__OM uint32_t ITM_Type::IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

◆ LAR

__OM uint32_t ITM_Type::LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

◆ LSR

__IM uint32_t ITM_Type::LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

◆ 

__OM union { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

◆ TCR

__IOM uint32_t ITM_Type::TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

◆ TER

__IOM uint32_t ITM_Type::TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

◆ TPR

__IOM uint32_t ITM_Type::TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

◆ u16

__OM uint16_t ITM_Type::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

◆ u32

__OM uint32_t ITM_Type::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

◆ u8

__OM uint8_t ITM_Type::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit