PMU_Type Struct Reference

Structure type to access the Performance Monitoring Unit (PMU). More...

Data Fields
__IOM uint32_t	AUTHSTATUS
	PMU Authentication Status Register.
__IOM uint32_t	CCFILTR
	PMU Cycle Counter Filter Register.
__IOM uint32_t	CCNTR
	PMU Cycle Counter Register.
__IOM uint32_t	CIDR0
	PMU Component Identification Register 0.
__IOM uint32_t	CIDR1
	PMU Component Identification Register 1.
__IOM uint32_t	CIDR2
	PMU Component Identification Register 2.
__IOM uint32_t	CIDR3
	PMU Component Identification Register 3.
__IOM uint32_t	CNTENCLR
	PMU Count Enable Clear Register.
__IOM uint32_t	CNTENSET
	PMU Count Enable Set Register.
__IOM uint32_t	CTRL
	PMU Control Register.
__IOM uint32_t	DEVARCH
	PMU Device Architecture Register.
__IOM uint32_t	DEVTYPE
	PMU Device Type Register.
__IOM uint32_t	EVCNTR [__PMU_NUM_EVENTCNT]
	PMU Event Counter Registers.
__IOM uint32_t	EVTYPER [__PMU_NUM_EVENTCNT]
	PMU Event Type and Filter Registers.
__IOM uint32_t	INTENCLR
	PMU Interrupt Enable Clear Register.
__IOM uint32_t	INTENSET
	PMU Interrupt Enable Set Register.
__IOM uint32_t	OVSCLR
	PMU Overflow Flag Status Clear Register.
__IOM uint32_t	OVSSET
	PMU Overflow Flag Status Set Register.
__IOM uint32_t	PIDR0
	PMU Peripheral Identification Register 0.
__IOM uint32_t	PIDR1
	PMU Peripheral Identification Register 1.
__IOM uint32_t	PIDR2
	PMU Peripheral Identification Register 2.
__IOM uint32_t	PIDR3
	PMU Peripheral Identification Register 3.
__IOM uint32_t	PIDR4
	PMU Peripheral Identification Register 4.
__IOM uint32_t	SWINC
	PMU Software Increment Register.
__IOM uint32_t	TYPE
	PMU Type Register.

Description

Structure type to access the Performance Monitoring Unit (PMU).

Field Documentation

AUTHSTATUS

__IOM uint32_t PMU_Type::AUTHSTATUS

PMU Authentication Status Register.

Offset: 0xFB8 (R/W) Authentication Status Register.

Offset: 0xFB8 (R/W)

CCFILTR

__IOM uint32_t PMU_Type::CCFILTR

PMU Cycle Counter Filter Register.

Offset: 0x47C (R/W) Cycle Counter Filter Register.

Offset: 0x47C (R/W)

CCNTR

__IOM uint32_t PMU_Type::CCNTR

PMU Cycle Counter Register.

Offset: 0x7C (R/W) Cycle Counter Register.

Offset: 0x7C (R/W)

CIDR0

__IOM uint32_t PMU_Type::CIDR0

PMU Component Identification Register 0.

Offset: 0xFF0 (R/W)

CIDR1

__IOM uint32_t PMU_Type::CIDR1

PMU Component Identification Register 1.

Offset: 0xFF4 (R/W)

CIDR2

__IOM uint32_t PMU_Type::CIDR2

PMU Component Identification Register 2.

Offset: 0xFF8 (R/W)

CIDR3

__IOM uint32_t PMU_Type::CIDR3

PMU Component Identification Register 3.

Offset: 0xFFC (R/W)

CNTENCLR

__IOM uint32_t PMU_Type::CNTENCLR

PMU Count Enable Clear Register.

Offset: 0xC20 (R/W) Count Enable Clear Register.

Offset: 0xC20 (R/W)

CNTENSET

__IOM uint32_t PMU_Type::CNTENSET

PMU Count Enable Set Register.

Offset: 0xC00 (R/W) Count Enable Set Register.

Offset: 0xC00 (R/W)

CTRL

__IOM uint32_t PMU_Type::CTRL

PMU Control Register.

Offset: 0xE04 (R/W) Control Register.

Offset: 0xE04 (R/W)

DEVARCH

__IOM uint32_t PMU_Type::DEVARCH

PMU Device Architecture Register.

Offset: 0xFBC (R/W) Device Architecture Register.

Offset: 0xFBC (R/W)

DEVTYPE

__IOM uint32_t PMU_Type::DEVTYPE

PMU Device Type Register.

Offset: 0xFCC (R/W) Device Type Register.

Offset: 0xFCC (R/W)

EVCNTR

__IOM uint32_t PMU_Type::EVCNTR

PMU Event Counter Registers.

Offset: 0x0 (R/W) Event Counter Registers.

Offset: 0x0 (R/W)

Two up to 31 event counters, see device specific __PMU_NUM_EVENTCNT

EVTYPER

__IOM uint32_t PMU_Type::EVTYPER

PMU Event Type and Filter Registers.

Offset: 0x400 (R/W) Event Type and Filter Registers.

Offset: 0x400 (R/W)

Two up to 31 event counters, see device specific __PMU_NUM_EVENTCNT

INTENCLR

__IOM uint32_t PMU_Type::INTENCLR

PMU Interrupt Enable Clear Register.

Offset: 0xC60 (R/W) Interrupt Enable Clear Register.

Offset: 0xC60 (R/W)

INTENSET

__IOM uint32_t PMU_Type::INTENSET

PMU Interrupt Enable Set Register.

Offset: 0xC40 (R/W) Interrupt Enable Set Register.

Offset: 0xC40 (R/W)

OVSCLR

__IOM uint32_t PMU_Type::OVSCLR

PMU Overflow Flag Status Clear Register.

Offset: 0xC80 (R/W) Overflow Flag Status Clear Register.

Offset: 0xC80 (R/W)

OVSSET

__IOM uint32_t PMU_Type::OVSSET

PMU Overflow Flag Status Set Register.

Offset: 0xCC0 (R/W) Overflow Flag Status Set Register.

Offset: 0xCC0 (R/W)

PIDR0

__IOM uint32_t PMU_Type::PIDR0

PMU Peripheral Identification Register 0.

Offset: 0xFE0 (R/W)

PIDR1

__IOM uint32_t PMU_Type::PIDR1

PMU Peripheral Identification Register 1.

Offset: 0xFE4 (R/W)

PIDR2

__IOM uint32_t PMU_Type::PIDR2

PMU Peripheral Identification Register 2.

Offset: 0xFE8 (R/W)

PIDR3

__IOM uint32_t PMU_Type::PIDR3

PMU Peripheral Identification Register 3.

Offset: 0xFEC (R/W)

PIDR4

__IOM uint32_t PMU_Type::PIDR4

PMU Peripheral Identification Register 4.

Offset: 0xFD0 (R/W)

SWINC

__IOM uint32_t PMU_Type::SWINC

PMU Software Increment Register.

Offset: 0xCA0 (R/W) Software Increment Register.

Offset: 0xCA0 (R/W)

TYPE

__IOM uint32_t PMU_Type::TYPE

PMU Type Register.

Offset: 0xE00 (R/W) Type Register.

Offset: 0xE00 (R/W)