CMSIS-Core (Cortex-M)  
CMSIS-Core support for Cortex-M processor-based devices
 
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TPIU_Type Struct Reference

Structure type to access the Trace Port Interface Register (TPI). More...

Data Fields

__IOM uint32_t ACPR
 Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.
 
__IOM uint32_t CLAIMCLR
 Offset: 0xFA4 (R/W) Claim tag clear.
 
__IOM uint32_t CLAIMSET
 Offset: 0xFA0 (R/W) Claim tag set.
 
__IOM uint32_t CSPSR
 Offset: 0x004 (R/W) Current Parallel Port Size Register.
 
__IM uint32_t DEVID
 Offset: 0xFC8 (R/ ) TPIU_DEVID.
 
__IM uint32_t DEVTYPE
 Offset: 0xFCC (R/ ) TPIU_DEVTYPE.
 
__IOM uint32_t FFCR
 Offset: 0x304 (R/W) Formatter and Flush Control Register.
 
__IM uint32_t FFSR
 Offset: 0x300 (R/ ) Formatter and Flush Status Register.
 
__IM uint32_t FIFO0
 Offset: 0xEEC (R/ ) Integration ETM Data.
 
__IM uint32_t FIFO1
 Offset: 0xEFC (R/ ) Integration ITM Data.
 
__IM uint32_t FSCR
 Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.
 
__IM uint32_t ITATBCTR0
 Offset: 0xEF8 (R/ ) ITATBCTR0.
 
__IM uint32_t ITATBCTR2
 Offset: 0xEF0 (R/ ) ITATBCTR2.
 
__IOM uint32_t ITCTRL
 Offset: 0xF00 (R/W) Integration Mode Control.
 
__IOM uint32_t SPPR
 Offset: 0x0F0 (R/W) Selected Pin Protocol Register.
 
__IOM uint32_t SSPSR
 Offset: 0x000 (R/ ) Supported Parallel Port Size Register.
 
__IM uint32_t TRIGGER
 Offset: 0xEE8 (R/ ) TRIGGER.
 

Description

Structure type to access the Trace Port Interface Register (TPI).

Field Documentation

◆ ACPR

__IOM uint32_t TPIU_Type::ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.

◆ CLAIMCLR

__IOM uint32_t TPIU_Type::CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear.

◆ CLAIMSET

__IOM uint32_t TPIU_Type::CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set.

◆ CSPSR

__IOM uint32_t TPIU_Type::CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register.

◆ DEVID

__IM uint32_t TPIU_Type::DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID.

◆ DEVTYPE

__IM uint32_t TPIU_Type::DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE.

◆ FFCR

__IOM uint32_t TPIU_Type::FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register.

◆ FFSR

__IM uint32_t TPIU_Type::FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register.

◆ FIFO0

__IM uint32_t TPIU_Type::FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data.

◆ FIFO1

__IM uint32_t TPIU_Type::FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data.

◆ FSCR

__IM uint32_t TPIU_Type::FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.

◆ ITATBCTR0

__IM uint32_t TPIU_Type::ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0.

◆ ITATBCTR2

__IM uint32_t TPIU_Type::ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2.

◆ ITCTRL

__IOM uint32_t TPIU_Type::ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control.

◆ SPPR

__IOM uint32_t TPIU_Type::SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register.

◆ SSPSR

__IOM uint32_t TPIU_Type::SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register.

◆ TRIGGER

__IM uint32_t TPIU_Type::TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER.