Bit position and mask macros. More...
Macros | |
| #define | ACTLR_DDI_Pos 28U |
| ACTLR: DDI Position. | |
| #define | ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) |
| ACTLR: DDI Mask. | |
| #define | ACTLR_DBDI_Pos 28U |
| ACTLR: DBDI Position. | |
| #define | ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) |
| ACTLR: DBDI Mask. | |
| #define | ACTLR_BTDIS_Pos 18U |
| ACTLR: BTDIS Position. | |
| #define | ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) |
| ACTLR: BTDIS Mask. | |
| #define | ACTLR_RSDIS_Pos 17U |
| ACTLR: RSDIS Position. | |
| #define | ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) |
| ACTLR: RSDIS Mask. | |
| #define | ACTLR_BP_Pos 15U |
| ACTLR: BP Position. | |
| #define | ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) |
| ACTLR: BP Mask. | |
| #define | ACTLR_DDVM_Pos 15U |
| ACTLR: DDVM Position. | |
| #define | ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) |
| ACTLR: DDVM Mask. | |
| #define | ACTLR_L1PCTL_Pos 13U |
| ACTLR: L1PCTL Position. | |
| #define | ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) |
| ACTLR: L1PCTL Mask. | |
| #define | ACTLR_RADIS_Pos 12U |
| ACTLR: RADIS Position. | |
| #define | ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) |
| ACTLR: RADIS Mask. | |
| #define | ACTLR_L1RADIS_Pos 12U |
| ACTLR: L1RADIS Position. | |
| #define | ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) |
| ACTLR: L1RADIS Mask. | |
| #define | ACTLR_DWBST_Pos 11U |
| ACTLR: DWBST Position. | |
| #define | ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) |
| ACTLR: DWBST Mask. | |
| #define | ACTLR_L2RADIS_Pos 11U |
| ACTLR: L2RADIS Position. | |
| #define | ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) |
| ACTLR: L2RADIS Mask. | |
| #define | ACTLR_DODMBS_Pos 10U |
| ACTLR: DODMBS Position. | |
| #define | ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) |
| ACTLR: DODMBS Mask. | |
| #define | ACTLR_PARITY_Pos 9U |
| ACTLR: PARITY Position. | |
| #define | ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) |
| ACTLR: PARITY Mask. | |
| #define | ACTLR_AOW_Pos 8U |
| ACTLR: AOW Position. | |
| #define | ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) |
| ACTLR: AOW Mask. | |
| #define | ACTLR_EXCL_Pos 7U |
| ACTLR: EXCL Position. | |
| #define | ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) |
| ACTLR: EXCL Mask. | |
| #define | ACTLR_SMP_Pos 6U |
| ACTLR: SMP Position. | |
| #define | ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) |
| ACTLR: SMP Mask. | |
| #define | ACTLR_WFLZM_Pos 3U |
| ACTLR: WFLZM Position. | |
| #define | ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) |
| ACTLR: WFLZM Mask. | |
| #define | ACTLR_L1PE_Pos 2U |
| ACTLR: L1PE Position. | |
| #define | ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) |
| ACTLR: L1PE Mask. | |
| #define | ACTLR_FW_Pos 0U |
| ACTLR: FW Position. | |
| #define | ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) |
| ACTLR: FW Mask. | |
Bit position and mask macros.
| #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) |
ACTLR: AOW Mask.
| #define ACTLR_AOW_Pos 8U |
ACTLR: AOW Position.
| #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) |
ACTLR: BP Mask.
| #define ACTLR_BP_Pos 15U |
ACTLR: BP Position.
| #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) |
ACTLR: BTDIS Mask.
| #define ACTLR_BTDIS_Pos 18U |
ACTLR: BTDIS Position.
| #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) |
ACTLR: DBDI Mask.
| #define ACTLR_DBDI_Pos 28U |
ACTLR: DBDI Position.
| #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) |
ACTLR: DDI Mask.
| #define ACTLR_DDI_Pos 28U |
ACTLR: DDI Position.
| #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) |
ACTLR: DDVM Mask.
| #define ACTLR_DDVM_Pos 15U |
ACTLR: DDVM Position.
| #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) |
ACTLR: DODMBS Mask.
| #define ACTLR_DODMBS_Pos 10U |
ACTLR: DODMBS Position.
| #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) |
ACTLR: DWBST Mask.
| #define ACTLR_DWBST_Pos 11U |
ACTLR: DWBST Position.
| #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) |
ACTLR: EXCL Mask.
| #define ACTLR_EXCL_Pos 7U |
ACTLR: EXCL Position.
| #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) |
ACTLR: FW Mask.
| #define ACTLR_FW_Pos 0U |
ACTLR: FW Position.
| #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) |
ACTLR: L1PCTL Mask.
| #define ACTLR_L1PCTL_Pos 13U |
ACTLR: L1PCTL Position.
| #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) |
ACTLR: L1PE Mask.
| #define ACTLR_L1PE_Pos 2U |
ACTLR: L1PE Position.
| #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) |
ACTLR: L1RADIS Mask.
| #define ACTLR_L1RADIS_Pos 12U |
ACTLR: L1RADIS Position.
| #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) |
ACTLR: L2RADIS Mask.
| #define ACTLR_L2RADIS_Pos 11U |
ACTLR: L2RADIS Position.
| #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) |
ACTLR: PARITY Mask.
| #define ACTLR_PARITY_Pos 9U |
ACTLR: PARITY Position.
| #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) |
ACTLR: RADIS Mask.
| #define ACTLR_RADIS_Pos 12U |
ACTLR: RADIS Position.
| #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) |
ACTLR: RSDIS Mask.
| #define ACTLR_RSDIS_Pos 17U |
ACTLR: RSDIS Position.
| #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) |
ACTLR: SMP Mask.
| #define ACTLR_SMP_Pos 6U |
ACTLR: SMP Position.
| #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) |
ACTLR: WFLZM Mask.
| #define ACTLR_WFLZM_Pos 3U |
ACTLR: WFLZM Position.