CMSIS-Core (Cortex-A)  
CMSIS-Core support for Cortex-A processor-based devices
 
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Bit position and mask macros. More...

Macros

#define IFSR_ExT_Pos   12U
 IFSR: ExT Position.
 
#define IFSR_ExT_Msk   (1UL << IFSR_ExT_Pos)
 IFSR: ExT Mask.
 
#define IFSR_LPAE_Pos   9U
 IFSR: LPAE Position.
 
#define IFSR_LPAE_Msk   (0x1UL << IFSR_LPAE_Pos)
 IFSR: LPAE Mask.
 
#define IFSR_FS1_Pos   10U
 IFSR: FS1 Position.
 
#define IFSR_FS1_Msk   (1UL << IFSR_FS1_Pos)
 IFSR: FS1 Mask.
 
#define IFSR_FS0_Pos   0U
 IFSR: FS0 Position.
 
#define IFSR_FS0_Msk   (0xFUL << IFSR_FS0_Pos)
 IFSR: FS0 Mask.
 
#define IFSR_STATUS_Pos   0U
 IFSR: STATUS Position.
 
#define IFSR_STATUS_Msk   (0x3FUL << IFSR_STATUS_Pos)
 IFSR: STATUS Mask.
 

Description

Bit position and mask macros.

Macro Definition Documentation

◆ IFSR_ExT_Msk

#define IFSR_ExT_Msk   (1UL << IFSR_ExT_Pos)

IFSR: ExT Mask.

◆ IFSR_ExT_Pos

#define IFSR_ExT_Pos   12U

IFSR: ExT Position.

◆ IFSR_FS0_Msk

#define IFSR_FS0_Msk   (0xFUL << IFSR_FS0_Pos)

IFSR: FS0 Mask.

◆ IFSR_FS0_Pos

#define IFSR_FS0_Pos   0U

IFSR: FS0 Position.

◆ IFSR_FS1_Msk

#define IFSR_FS1_Msk   (1UL << IFSR_FS1_Pos)

IFSR: FS1 Mask.

◆ IFSR_FS1_Pos

#define IFSR_FS1_Pos   10U

IFSR: FS1 Position.

◆ IFSR_LPAE_Msk

#define IFSR_LPAE_Msk   (0x1UL << IFSR_LPAE_Pos)

IFSR: LPAE Mask.

◆ IFSR_LPAE_Pos

#define IFSR_LPAE_Pos   9U

IFSR: LPAE Position.

◆ IFSR_STATUS_Msk

#define IFSR_STATUS_Msk   (0x3FUL << IFSR_STATUS_Pos)

IFSR: STATUS Mask.

◆ IFSR_STATUS_Pos

#define IFSR_STATUS_Pos   0U

IFSR: STATUS Position.