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CMSIS-Core (Cortex-A)
CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A)
CMSIS-Core support for Cortex-A processor-based devices
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Bit field declaration for ACTLR layout. More...
#include <core_ca.h>
Data Fields | |
| struct { | |
| uint32_t FW:1 | |
| bit: 0 Cache and TLB maintenance broadcast More... | |
| uint32_t SMP:1 | |
| bit: 6 Enables coherent requests to the processor More... | |
| uint32_t EXCL:1 | |
| bit: 7 Exclusive L1/L2 cache control More... | |
| uint32_t DODMBS:1 | |
| bit: 10 Disable optimized data memory barrier behavior More... | |
| uint32_t DWBST:1 | |
| bit: 11 AXI data write bursts to Normal memory More... | |
| uint32_t RADIS:1 | |
| bit: 12 L1 Data Cache read-allocate mode disable More... | |
| uint32_t L1PCTL:2 | |
| bit:13..14 L1 Data prefetch control More... | |
| uint32_t BP:2 | |
| bit:16..15 Branch prediction policy More... | |
| uint32_t RSDIS:1 | |
| bit: 17 Disable return stack operation More... | |
| uint32_t BTDIS:1 | |
| bit: 18 Disable indirect Branch Target Address Cache (BTAC) More... | |
| uint32_t DBDI:1 | |
| bit: 28 Disable branch dual issue More... | |
| } | b |
| Structure used for bit access on Cortex-A5. | |
| struct { | |
| uint32_t SMP:1 | |
| bit: 6 Enables coherent requests to the processor More... | |
| uint32_t DODMBS:1 | |
| bit: 10 Disable optimized data memory barrier behavior More... | |
| uint32_t L2RADIS:1 | |
| bit: 11 L2 Data Cache read-allocate mode disable More... | |
| uint32_t L1RADIS:1 | |
| bit: 12 L1 Data Cache read-allocate mode disable More... | |
| uint32_t L1PCTL:2 | |
| bit:13..14 L1 Data prefetch control More... | |
| uint32_t DDVM:1 | |
| bit: 15 Disable Distributed Virtual Memory (DVM) transactions More... | |
| uint32_t DDI:1 | |
| bit: 28 Disable dual issue More... | |
| } | b |
| Structure used for bit access on Cortex-A7. | |
| struct { | |
| uint32_t FW:1 | |
| bit: 0 Cache and TLB maintenance broadcast More... | |
| uint32_t L1PE:1 | |
| bit: 2 Dside prefetch More... | |
| uint32_t WFLZM:1 | |
| bit: 3 Cache and TLB maintenance broadcast More... | |
| uint32_t SMP:1 | |
| bit: 6 Enables coherent requests to the processor More... | |
| uint32_t EXCL:1 | |
| bit: 7 Exclusive L1/L2 cache control More... | |
| uint32_t AOW:1 | |
| bit: 8 Enable allocation in one cache way only More... | |
| uint32_t PARITY:1 | |
| bit: 9 Support for parity checking, if implemented More... | |
| } | b |
| Structure used for bit access on Cortex-A9. | |
| uint32_t | w |
| Type used for word access. | |
Bit field declaration for ACTLR layout.
| uint32_t ACTLR_Type::AOW |
bit: 8 Enable allocation in one cache way only
| struct { ... } ACTLR_Type::b |
Structure used for bit access on Cortex-A5.
| struct { ... } ACTLR_Type::b |
Structure used for bit access on Cortex-A7.
| struct { ... } ACTLR_Type::b |
Structure used for bit access on Cortex-A9.
| uint32_t ACTLR_Type::BP |
bit:16..15 Branch prediction policy
| uint32_t ACTLR_Type::BTDIS |
bit: 18 Disable indirect Branch Target Address Cache (BTAC)
| uint32_t ACTLR_Type::DBDI |
bit: 28 Disable branch dual issue
| uint32_t ACTLR_Type::DDI |
bit: 28 Disable dual issue
| uint32_t ACTLR_Type::DDVM |
bit: 15 Disable Distributed Virtual Memory (DVM) transactions
| uint32_t ACTLR_Type::DODMBS |
bit: 10 Disable optimized data memory barrier behavior
| uint32_t ACTLR_Type::DWBST |
bit: 11 AXI data write bursts to Normal memory
| uint32_t ACTLR_Type::EXCL |
bit: 7 Exclusive L1/L2 cache control
| uint32_t ACTLR_Type::FW |
bit: 0 Cache and TLB maintenance broadcast
| uint32_t ACTLR_Type::L1PCTL |
bit:13..14 L1 Data prefetch control
| uint32_t ACTLR_Type::L1PE |
bit: 2 Dside prefetch
| uint32_t ACTLR_Type::L1RADIS |
bit: 12 L1 Data Cache read-allocate mode disable
| uint32_t ACTLR_Type::L2RADIS |
bit: 11 L2 Data Cache read-allocate mode disable
| uint32_t ACTLR_Type::PARITY |
bit: 9 Support for parity checking, if implemented
| uint32_t ACTLR_Type::RADIS |
bit: 12 L1 Data Cache read-allocate mode disable
| uint32_t ACTLR_Type::RSDIS |
bit: 17 Disable return stack operation
| uint32_t ACTLR_Type::SMP |
bit: 6 Enables coherent requests to the processor
| uint32_t ACTLR_Type::w |
Type used for word access.
| uint32_t ACTLR_Type::WFLZM |
bit: 3 Cache and TLB maintenance broadcast