Physical Timer Control register. More...
#include <core_ca.h>
Data Fields | |
struct { | |
uint32_t ENABLE:1 | |
bit: 0 Enables the timer. More... | |
uint32_t IMASK:1 | |
bit: 1 Timer output signal mask bit. More... | |
uint32_t ISTATUS:1 | |
bit: 2 The status of the timer. More... | |
} | b |
Structure used for bit access. | |
uint32_t | w |
Type used for word access. | |
struct { | |
uint32_t ENABLE:1 | |
bit: 0 Enables the timer. More... | |
uint32_t IMASK:1 | |
bit: 1 Timer output signal mask bit. More... | |
uint32_t ISTATUS:1 | |
bit: 2 The status of the timer. More... | |
uint32_t _reserved0:29 | |
bit: 3..31 Reserved More... | |
} | b |
Structure used for bit access. | |
Physical Timer Control register.
uint32_t CNTP_CTL_Type::_reserved0 |
bit: 3..31 Reserved
struct { ... } CNTP_CTL_Type::b |
Structure used for bit access.
struct { ... } CNTP_CTL_Type::b |
Structure used for bit access.
uint32_t CNTP_CTL_Type::ENABLE |
bit: 0 Enables the timer.
Enables the timer.
Permitted values are:
uint32_t CNTP_CTL_Type::IMASK |
bit: 1 Timer output signal mask bit.
Timer output signal mask bit.
Permitted values are:
uint32_t CNTP_CTL_Type::ISTATUS |
bit: 2 The status of the timer.
The status of the timer.
This bit indicates whether the timer condition is asserted:
uint32_t CNTP_CTL_Type::w |
Type used for word access.